Sequential Processor Golden Model

I. DEFINITION

- executes one instruction at a time.

- interface:
module seq_core(
      // general
    input         rst,   // active 0
    input         clk,
      // instruction port
    output [9:0]  instr_address,
    input [15:0]  instruction,
      // data port
    output        read,  // active 1
    output        write, // active 1
    output  [9:0] address,
    input  [15:0] data_in,
    output [15:0] data_out
);

- reset clears all registers and flags

- instructions have opcode fields defined through macros.
Example:
'define	ADD 5'b00001

- registers have numerical values defined through macros
Example:
'define R5 3'd5

- instructions are presented to the core in test files as assembler macros
Example:
instr = {'ADD, 'R2, 'R1, 'R0} // ADD R2 R1 R0

- instruction processing can be multicicle to allow for data memory accesses after instruction fetch

- memory address is taken from the lower 10 bits of the register given as address operand. 

II. ASSIGNMENTS

- write seq_core module behavioral description;

- write tests to check that each instruction type is properly executed for random operands values;

- write tests for simple sequences of instructions (a multiply algorithm);

- instructions and data are provided by tests as input stimuli.