Step by step Dynamic Scheduling design and verification - B (Register renaming)

1. Internal (physical) register file has 16 registers.
Each register has a valid state bit and a 4 bit counter (both set to 0 at reset).

2. The register map has 8 entries, each entry mapping an architectural register (R0, ..., R7)
to a physical one (r0, ..., r15).
The register map translates simultaneosly up to 3 architectural registers (one destination, two sources).
The reset value for each entry is its address value (entry 0 set to 0, entry 1 set to 1 a.s.o.).

3. During the decode stage the 3-bit architectural destination and source addresses are translated to
the 4-bit physical register addresses. The destination physical register must be free. Otherwise the first free register
is chosen to replace the architectural register and the register map is updated accordingly.
If there is no free register in the register set, the pipeline is stalled at this and fetch stages.

4. A register is free if it is not used by other entries in the register map and if its counter is zero.

5. The register counter is incremented whenever an instruction that uses it as source enters the read stage,
and decremented whenever an instruction reads it and passes to the execution stage.

6. The destination register is marked invalid upon reservation. The valid bit is set when the instruction 
that has reserved it writes its result.