Step by step Dynamic Scheduling design and verification - C (Instruction window)

1. Up to 12 instructions may be in the read, execution or write-back stages, some of them blocked in the read stage.
Some instructions that entered the pipeline after the oldest and before the newest instructions that are currently
in various processing stages may have already finished their processing,
therefore the instructions in the instruction window may at times be not contiguous. 

2. The instruction window (IW) is a buffer of 12 instructions.
Each register of the IW has the following fields:
- operation
- destination (4 bit)
- source 1 (4 bit)
- valid 1
- source 2 (4 bit)
- valid 2
- state (2 bits)
- age (6 bits)

3. The state of an instruction may be FREE (0), READ (1), EXECUTE (2), or WRITE-BACK (3). The state is a 2 bit counter
set to FREE at the reset. It is incremented any time an instruction advances to the read, execute, write-back stage,
and when it exits the pipeline (finishes the write-back stage). The instructions at the execute and write-back stages
carry with them their position in the Instruction Window buffer, so that the instruction state could be changed by them.

4. Any free register in the IW may be used to receive a new instruction from the decoder. If there are no free
entries in the IW, the decode and fetch stages are stalled.

5. An instruction is ready for execution if all its sources are valid.

6. If more than one instructions are ready for execution, only one of them is issued according to a round robin selection.

7. During the write-back stage the instruction writes its result into the destination register
and validates the valid bit for any instruction in the READ state that waits that result
(whose source address equals the destination of the result).

8. Upon entering the IW, the instruction sets to 0 its age counter. After that the age counter is incremented at each clock
cycle, so as to reflect the time spent by the instruction inside the IW. The age counters are used by the jump instructions
when the need arises to flush all newer instructions from the pipeline.
Be aware that if an instruction in the READ state is changed to NOP as a result of flushing,
its source addresses must pe processed as usual in order to properly decrement the counters
of the associated registers (the valid bit is ignored). Otherwise some registers will be stucked forever.
The flushed instructions have no results and must not change the registers values
(except for the abovementioned counter decrementing). It is better to retire a NOP instruction immediately after
it has succeded to decrement the counters of its sources, so that to free its entry in the IW (jump from READ state
to FREE state).