WikiLabs - Contribuții utilizator [ro]

Applications 5

2020-03-20T15:07:16Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1'''
Top level design

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''
the DIGIT SUM block

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, in the range of [0... 9], giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level ( a0 is ignored by the comparator, it is not conected as the figure shows:

'''Figure 3'''
the comparator

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:53:57Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1'''
(Top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''
( the DIGIT SUM block )

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, in the range of [0... 9], giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level ( a0 is ignored by the comparator, it is not conected as the figure shows:

'''Figure 3'''
( the comparator )

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:51:56Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1'''
(Top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''
( the DIGIT SUM block )

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, in the range of [0... 9], giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level ( a0 is ignored by the comparator, it is not conected as the figure shows:

'''Figure 3'''
( the comparator )

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:50:52Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1'''
(Top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''
( the DIGIT SUM block )

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, in the range of [0... 9], giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level ( a0 is ignored by the comparator, it is not conected as the figure shows:

'''Figure 3''' ( the comparator )

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:49:53Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1'''
(Top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''
( the DIGIT SUM block )

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, in the range of [0... 9], giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level ( a0 is ignored by the comparator, it is not conected as the figure shows:

'''Figure 3'''

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:22:18Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1''' .
(Top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''.
( the DIGIT SUM block )

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level:

'''Figure 3'''

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:20:58Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1''' .
(top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''.
( the DIGIT SUM block )

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level:

'''Figure 3'''

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:15:56Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1'''
(top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''
( the DIGIT SUM block )

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level:

'''Figure 3'''

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:14:02Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1''' (top level design)

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level:

'''Figure 3'''

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Applications 5

2020-03-20T14:12:11Z

Vdragomir: /* Description */

== Description ==
Design and verify a decimal adder with 2 digit input numbers.

The top level design (Figure 1) has 2 blocks, of type '''digitsum''', each block adding digits of the same range.

'''Figure 1'''

[[Fișier: bcdsum.png]]

The '''digitsum''' block (Figure 2) comprises 4 subblocks, two 4 bit binary adders, instances of '''sum4''', one instance of '''cmp''' and a simple 2 to 1 multiplexer.

'''Figure 2'''

[[Fișier: digit.png]]

The first adder adds the 4 bit inputs, giving a binary result in the range [0 ... 18].

The comparator, '''cmp''', outputs 1 if the result is greater than 9.

If the result is not greater than 9, than it is sent out directly to the '''digit''' output of the '''digitsum''' block (the result MSB is thrown away).

If the result is greater than 9, a correction must be made, adding 6 to the result.

The comparator with 9, '''cmp''', is described at the gate level:

'''Figure 3'''

[[Fișier: cmp.png]]

=== Testbench ===

The testbench must generate stimuli for '''bcdsum''' as in Figure 4.

b0 input of '''bcdsum''' changes at each 5 simulation steps.

b1, a0 and a1 change synchronously with b0 as in figure 4.

'''Figure 4'''

[[Fișier: teststimuli.png]]

== Requirements ==

# '''cmp''' module is described structurally at the gate level as in Figure 3.
# '''sum4''' module is described behaviorally with a continuous assignment.
# '''mux''' module is described behaviorally within an '''always''' process.
# '''digitsum''' module is described structurally as in Figure 2. It has 4 instances of the proper type.
# the top-level design module, '''bcdsum''', is described structurally as in Figure 1.
# write the testbench module, '''bcdsum_tb''', that instantiates the top-level module '''bcdsum''' with the instance name '''dut'''.
# in the testbench, generate stimuli for the dut inputs.
# in the wave panel of the simulation change the radix to ''unsigned decimal'' and zoom full.

=== Interfaces ===
cmp(a, gt)

mux(y, sel, i1, i0)

sum4(a, b, c, s)

digitsum(a, b, ci, co, digit)

bcdsum(a1, a0, b1, b0, s2, s1, s0)

bcdsum_tb // the testbench module has no pins

Pagina principală

2020-02-22T21:41:07Z

Vdragomir: /* Materiale pentru seminar */

Scopul acestei pagini este de a centraliza platformele de laborator dar și toate resursele auxiliare pentru cursurile și laboratoarele ținute în cadrul departamentului de Dispozitive, Circuite și Arhitecturi Electronice.

== Materiale de curs ==
* [[Programarea Calculatoarelor (curs seria C,F)|Programarea Calculatoarelor]]
* [[Circuite Integrate Digitale (curs)|Circuite Integrate Digitale]]
* [[Dispozitive Semiconductoare de Putere (curs)|Dispozitive Semiconductoare de Putere]]
* [[Structuri de Date și Algoritmi (curs)|Structuri de Date și Algoritmi]]
* [[Senzori si Circuite de Conditionare a Semnalelor (curs)|Senzori si Circuite de Conditionare a Semnalelor]]

* [[Programare Orientată Obiect (curs)|Programare Orientată Obiect]]
* [[Tehnici de proiectare VLSI (curs)|Tehnici de proiectare VLSI]]

== Platforme de laborator ==
* [[Arhitectura Sistemelor de Calcul]]
* [[Circuite Integrate Analogice (laborator)|Circuite Integrate Analogice]]
* [[Circuite Integrate Digitale (laborator)|Circuite Integrate Digitale]] * [[Digital Integrated Circuits (lab)|Digital Integrated Circuits]]
* [[Dispozitive Semiconductoare de Putere (laborator)|Dispozitive Semiconductoare de Putere]]
* [[Dispozitive Electronice(laborator)|Dispozitive Electronice]]
* [[Circuite Electronice(laborator)|Circuite Electronice]]
* [[Programare Orientată Obiect (Java)]]
* [[Programare Orientată pe Obiecte (C++)]]
* [[Structuri de Date și Algoritmi]]
* [[Senzori si Circuite de Conditionare a Semnalelor (laborator)|SCCS]]
* [[Programarea Calculatoarelor (laborator)|Programarea Calculatoarelor]]
* [[Tehnici de proiectare VLSI (laborator)|Tehnici de proiectare VLSI]]
* [[Performance analysis and optimization]]

== Materiale vechi CID ==
* [[Circuite integrate digitale (seminar)|Circuite Integrate Digitale]] * [[Digital Integrated Circuits (seminar)|Digital Integrated Circuits]]

== Materiale pentru aplicatii ==
* [[Digital Integrated Circuits ]]

== Materiale pentru proiecte ==
* [[Project SCCS - Senzori si Circuite de Conditionare a Semnalelor]]
* [[Proiect 1 - Dispozitive si Circuite Electronice|Dispozitive si Circuite Electronice]]

== Regulamente ==
* [[Regulament protectia muncii]]
* [[Regulamentul laboratoarelor POO și ASC]]

Pagina principală

2020-02-22T21:37:53Z

Vdragomir:

Scopul acestei pagini este de a centraliza platformele de laborator dar și toate resursele auxiliare pentru cursurile și laboratoarele ținute în cadrul departamentului de Dispozitive, Circuite și Arhitecturi Electronice.

== Materiale de curs ==
* [[Programarea Calculatoarelor (curs seria C,F)|Programarea Calculatoarelor]]
* [[Circuite Integrate Digitale (curs)|Circuite Integrate Digitale]]
* [[Dispozitive Semiconductoare de Putere (curs)|Dispozitive Semiconductoare de Putere]]
* [[Structuri de Date și Algoritmi (curs)|Structuri de Date și Algoritmi]]
* [[Senzori si Circuite de Conditionare a Semnalelor (curs)|Senzori si Circuite de Conditionare a Semnalelor]]

* [[Programare Orientată Obiect (curs)|Programare Orientată Obiect]]
* [[Tehnici de proiectare VLSI (curs)|Tehnici de proiectare VLSI]]

== Platforme de laborator ==
* [[Arhitectura Sistemelor de Calcul]]
* [[Circuite Integrate Analogice (laborator)|Circuite Integrate Analogice]]
* [[Circuite Integrate Digitale (laborator)|Circuite Integrate Digitale]] * [[Digital Integrated Circuits (lab)|Digital Integrated Circuits]]
* [[Dispozitive Semiconductoare de Putere (laborator)|Dispozitive Semiconductoare de Putere]]
* [[Dispozitive Electronice(laborator)|Dispozitive Electronice]]
* [[Circuite Electronice(laborator)|Circuite Electronice]]
* [[Programare Orientată Obiect (Java)]]
* [[Programare Orientată pe Obiecte (C++)]]
* [[Structuri de Date și Algoritmi]]
* [[Senzori si Circuite de Conditionare a Semnalelor (laborator)|SCCS]]
* [[Programarea Calculatoarelor (laborator)|Programarea Calculatoarelor]]
* [[Tehnici de proiectare VLSI (laborator)|Tehnici de proiectare VLSI]]
* [[Performance analysis and optimization]]

== Materiale pentru seminar ==
* [[Circuite integrate digitale (seminar)|Circuite Integrate Digitale]] * [[Digital Integrated Circuits (seminar)|Digital Integrated Circuits]]

== Materiale pentru aplicatii ==
* [[Digital Integrated Circuits ]]

== Materiale pentru proiecte ==
* [[Project SCCS - Senzori si Circuite de Conditionare a Semnalelor]]
* [[Proiect 1 - Dispozitive si Circuite Electronice|Dispozitive si Circuite Electronice]]

== Regulamente ==
* [[Regulament protectia muncii]]
* [[Regulamentul laboratoarelor POO și ASC]]