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= Course sessions = Courses can be found on Moodle platform. = Lab sessions = * [[Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation]] * [[Lab 2 - Hardware flow. Vivado. PYNQ framework]] = Admin = * Course - 50p oral exam (to be discussed) * Lab ** 20p assignments (to be discussed) ** 30p project (to be discussed) Contact: alexandru.ulmamei@upb.ro = Useful resources = * [https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM ZYNQ7000 Technical Reference Manual] * [https://docs.amd.com/r/en-US/ug1399-vitis-hls High Level Synthesis User Guide] * [https://developer.arm.com/documentation/ihi0022/latest/ ARM AMBA Architecture] * [https://cse.usf.edu/~haozheng/teach/cda4253/doc/hls/hls_bluebook_uv.pdf High Level Synthesis Book]

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