Applications 1 - Revizia istoricului

Zhascsi la 23 februarie 2025 20:38

2025-02-23T20:38:46Z

Zhascsi: /* Ordered sequence of values */

2025-02-23T20:28:02Z

Ordered sequence of values

Zhascsi la 23 februarie 2025 19:50

2025-02-23T19:50:32Z

Zhascsi la 23 februarie 2025 18:59

2025-02-23T18:59:37Z

Zhascsi: /* One bit signal generation */

2025-02-23T18:58:48Z

One bit signal generation

Zhascsi: /* One bit signal generation */

2025-02-02T19:54:35Z

One bit signal generation

Zhascsi: /* Multi-bit signal generation */

2025-02-02T19:53:34Z

Multi-bit signal generation

Zhascsi: /* Two one-bit signals generation */

2025-02-02T19:51:52Z

Two one-bit signals generation

Zhascsi: /* Two one-bit signals generation */

2025-02-02T19:51:19Z

Two one-bit signals generation

Zhascsi: /* Two one-bit signals generation */

2025-02-02T19:49:44Z

Two one-bit signals generation

← Versiunea anterioară		Versiunea de la data 23 februarie 2025 20:38
Linia 194:		Linia 194:

	* Note: This last example runs through 16 iterations, such that the loop is exited with zero for data. The previous example runs only for 15 iterations because there is no way to write a condition for data to exit the loop after one more iteration (since all data values are valid and incrementing from 4'b1111 gives 4'b0000), therefore after the loop is exited data remains at the maximum value.		* Note: This last example runs through 16 iterations, such that the loop is exited with zero for data. The previous example runs only for 15 iterations because there is no way to write a condition for data to exit the loop after one more iteration (since all data values are valid and incrementing from 4'b1111 gives 4'b0000), therefore after the loop is exited data remains at the maximum value.
		+
		+	[[Fișier:Dic_lab1_sequence.png]]

	The last for loop may be condensed, grouping more assignments as ''initial_assignments'' and ''step_assignments'':		The last for loop may be condensed, grouping more assignments as ''initial_assignments'' and ''step_assignments'':

← Versiunea anterioară		Versiunea de la data 23 februarie 2025 20:28
Linia 178:		Linia 178:

	The above loop starts with zero. For each iteration it waits 10 simulation steps and increments data value. At the end of the 15'th iteration data value is incremented to 15 after which the expression <syntaxhighlight lang="SystemVerilog" inline>data < 15</syntaxhighlight> is evaluated to false and the loop statement is exited.		The above loop starts with zero. For each iteration it waits 10 simulation steps and increments data value. At the end of the 15'th iteration data value is incremented to 15 after which the expression <syntaxhighlight lang="SystemVerilog" inline>data < 15</syntaxhighlight> is evaluated to false and the loop statement is exited.
		+
		+	A more traditional approach when the number of iterations is fixed and known is to use an index for the loop that runs from 0 to the desired value. The index is a classic (borrowed from C) type of integer variable '''int''':
		+
		+	<syntaxhighlight lang="SystemVerilog">
		+	logic [3:0] data;
		+	int i;
		+
		+	initial begin
		+	data = 0;
		+	for(i = 0; i < 16; i++) begin
		+	#10 data++;
		+	end
		+	end
		+	</syntaxhighlight>
		+
		+	* Note: This last example runs through 16 iterations, such that the loop is exited with zero for data. The previous example runs only for 15 iterations because there is no way to write a condition for data to exit the loop after one more iteration (since all data values are valid and incrementing from 4'b1111 gives 4'b0000), therefore after the loop is exited data remains at the maximum value.
		+
		+	The last for loop may be condensed, grouping more assignments as ''initial_assignments'' and ''step_assignments'':
		+
		+	<syntaxhighlight lang="SystemVerilog">
		+	logic [3:0] data;
		+	int i;
		+
		+	initial begin
		+	for(i = 0, data = 0; i < 16; i++, data++) begin
		+	#10;
		+	end
		+	end
		+	</syntaxhighlight>

@@ Linia 144: / Linia 144: @@
 You may generate separate signals grouping them into a bundle and assigning multi-bit values to this bundle. Two or more signals can be bundled together using the concatenation operator, '''{ }'''. The bundled signals are listed inside the curly brackets of the concatenation operator, separated by commas. The signals' bits are arranged from left to right, in the order in which the signals are listed.
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial begin
          {a, b} = 2'b00; // a and b are both set to 0 at the beginning of simulation
@@ Linia 151: / Linia 151: @@
 end
 </syntaxhighlight>

@@ Linia 45: / Linia 45: @@
 <syntaxhighlight lang="SystemVerilog">
-module waveform1;
+module test;
 logic a;          // first signal declaration
@@ Linia 80: / Linia 80: @@
 <syntaxhighlight lang="SystemVerilog">
-module waveform1;
+module test;
 logic a, b;       // two variables of the same type (and width) may be declared in one declaration statement (not recommended)
@@ Linia 106: / Linia 106: @@
 <syntaxhighlight lang="SystemVerilog">
-module waveform1;
+module test;
 logic [1:0] data; // A 2-bit variable of type reg, named data. MSB index is 1, LSB index is 0

@@ Linia 21: / Linia 21: @@
 <syntaxhighlight lang="SystemVerilog">
-module waveform1; // module declaration. The testbench module is named waveform1 and has no ports (its generated signal is internal).
+module test; // module declaration. The testbench module is named test and has no ports (its generated signal is internal).
 logic a;          // signal declaration. Signal named a is a variable of type logic. The default size is one bit.

@@ Linia 105: / Linia 105: @@
 Multi-bit signal declaration sets the width of the signal using two indices. The left index is the index of the most significant bit (MSB), the right index is of the least significant bit (LSB)
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module waveform1;
-reg [1:0] data;   // A 2-bit variable of type reg, named data. MSB index is 1, LSB ndex is 0
+logic [1:0] data; // A 2-bit variable of type reg, named data. MSB index is 1, LSB index is 0
 initial begin
@@ Linia 114: / Linia 114: @@
       #5 data = 1; // after 5 simulation steps, data changes to 1
       #5 data = 3; // after other 5 steps, data changes to 3
-                   // more statements to change data value as desired                                  << COMPLETE THE MISSING CODE
+                   // more statements to change data value as desired                   << COMPLETE THE MISSING CODE
      #20 $stop;
 end
@@ Linia 121: / Linia 121: @@
 </syntaxhighlight>
-In the above code the data values are given as decimal integers. Verilog integer constants may be written in 4 bases: decimal, hexadecimal, octal and binary. The decimal base is implicit if only a plain number literal is written. To write the value in another base you should prefix the number literal with a base specifier, which is the apostrophe sign folowed by a letter that specifies the base: ''''d''' for decimal, ''''b''' for binary, ''''h''' for hexadecimal.
+In the above code the data values are given as decimal integers. SystemVerilog integer constants may be written in 4 bases: decimal, hexadecimal, octal and binary. The decimal base is implicit if only a plain number literal is written. To write the value in another base you should prefix the number literal with a base specifier, which is the apostrophe sign followed by a letter that specifies the base: ''''d''' for decimal, ''''b''' for binary, ''''h''' for hexadecimal.
 Generate the same sequence of data values using a binary number format:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial begin
          data = 2'b00; // data is set to 0 at the beginning of simulation

@@ Linia 44: / Linia 44: @@
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module waveform1;
-reg a;            // first signal declaration
+logic a;          // first signal declaration
-reg b;            // second signal declaration
+logic b;          // second signal declaration
 initial begin     // initial procedural block for the generation of a
@@ Linia 66: / Linia 66: @@
 </syntaxhighlight>
-Each verilog procedural block is treated as a thread by Vivado simulator. All procedural blocks are seen as parallel threads. When one thread finishes its execution, other threads may still have statements to execute. The '''initial''' block for generation of b executes its last statement at step 15. However the simulation goes forward (there are still statements in the other '''initial''' block to be executed). The stop should be called from the '''initial''' procedural block that is last to finish. Alternatively, you may employ a separate '''initial''' block to stop the simulation, using a delay whose value covers all steps of the simulation:
+Each procedural block is treated as a thread by Vivado simulator. All procedural blocks are seen as parallel threads. When one thread finishes its execution, other threads may still have statements to execute. The '''initial''' block for generation of b executes its last statement at step 15. However the simulation goes forward (there are still statements in the other '''initial''' block to be executed). The stop should be called from the '''initial''' procedural block that is last to finish. Alternatively, you may employ a separate '''initial''' block to stop the simulation, using a delay whose value covers all steps of the simulation:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial #40 $stop;
 </syntaxhighlight>