Applications 11 - Revizia istoricului

Zhascsi la 23 mai 2019 05:44

2019-05-23T05:44:12Z

Zhascsi: /* Design hints */

2019-05-22T11:56:53Z

Design hints

Zhascsi: /* Design hints */

2019-05-22T11:55:49Z

Design hints

Zhascsi: /* Description */

2019-05-22T11:27:31Z

Description

Zhascsi: Pagină nouă: == Requirement == ''Design, verify and implement a calculator. It adds, subtracts or multiplies an 8 bit number to/from the current content of its accumulator. It continuously disp...

2019-05-22T07:36:36Z

Pagină nouă: == Requirement == ''Design, verify and implement a calculator. It adds, subtracts or multiplies an 8 bit number to/from the current content of its accumulator. It continuously disp...

Pagină nouă

== Requirement ==
''Design, verify and implement a calculator. It adds, subtracts or multiplies an 8 bit number to/from the current content of its accumulator. It continuously display the input number (on the first two display digits) and the current content of the accumulator (on the last three digits of the display).''

== Description ==

The heart of the calculator is the FSM. It receives commands from the push buttons (''PLUS'', ''MINUS'', ''MULTIPLY'' or ''CLEAR''), and sends control signals to the datapath. Apart from the FSM there are 6 registers, one for storing the result (the '''accumulator'''), and one for each of the digits used for display. The inputs shown in red are the control signals generated by the FSM. The blocks colored in blue are sequential, clocked by the 50 MHz input clock and initialized/cleared by the common reset input. The reset is assimilated to the ''CLEAR'' command.

[[Fișier: calc.png]]

== Design hints ==

# For the BCD converter see Exercise 3 from Applications 4. Adapt that solution such that to convert an 8 bit binary number to a three digit BCD number.
# For the ROM module see Exercise 1 from Applications 8, or Applications 10
# The inputs '''bmul''', '''bsub''' and '''badd''' from the push buttons, being active 0, may be transformed to single pulse internal signals, in order to easy the FSM design:
<syntaxhighlight lang = "verilog">
reg button_d; // delayed button input
wire button_p; // one clock cycle pulse
always @(posedge clk)
button_d = button;
assign button_p = button & ~button_d; // one clock cycle pulse generated after the push button was released
</syntaxhighlight>

@@ Linia 45: / Linia 45: @@
 * If the inputs from push buttons are transformed to one clock cycle pulses, and supposing that the user presses one button at a time, these pulses may be directly used to control the accumulator update and to select the function of the FUNC block:
 assign lda = badd_p | bsub_p | bmult_p;
 assign selfunc = {badd_p,bsub_p,bmult_p};
 * selfunc values may be defined as localparameters (ADD, SUB etc) to make the code more readable and manageable.

← Versiunea anterioară		Versiunea de la data 22 mai 2019 11:27
Linia 9:		Linia 9:
	[[Fișier: calc.png]]		[[Fișier: calc.png]]

		+	The output display configuration is stored in 5 registers which are updated cyclically, with a rate of around 100 Hz. In order to use one BCD converter and one BCD-to-segment converter, the input and accumulator values, and their digits are multiplexed digit by digit. A simple solution may be based on a counter from which 3 bits are used to generate the required control signals, as in the figure below:
		+
		+	[[Fișier: appl11_mux_wave.png]]

	== Design hints ==		== Design hints ==

@@ Linia 1: / Linia 1: @@
 == Requirement ==
-''Design, verify and implement a calculator. It adds, subtracts or multiplies an 8 bit number to/from the current content of its accumulator. It continuously display the input number (on the first two display digits) and the current content of the accumulator (on the last three digits of the display).''
+''Design, verify and implement a calculator. It adds, subtracts or multiplies a 6 bit number to/from the current content of its accumulator. It continuously display the input number (on the first two display digits) and the current content of the accumulator (on the last three digits of the display). The accumulator's range is from 0 to 255.''
 == Description ==
-The heart of the calculator is the FSM. It receives commands from the push buttons (''PLUS'', ''MINUS'', ''MULTIPLY'' or ''CLEAR''), and sends control signals to the datapath. Apart from the FSM there are 6 registers, one for storing the result (the '''accumulator'''), and one for each of the digits used for display. The inputs shown in red are the control signals generated by the FSM. The blocks colored in blue are sequential, clocked by the 50 MHz input clock and initialized/cleared by the common reset input. The reset is assimilated to the ''CLEAR'' command.
+The heart of the calculator is the CTRL block. It receives commands from the push buttons (''PLUS'', ''MINUS'', ''MULTIPLY'' or ''CLEAR''), and sends control signals to the datapath. Apart from CTRL there are 6 registers, one for storing the result (the '''accumulator'''), and one for each of the digits used for display. The inputs shown in red are the control signals generated by the CTRL. The blocks colored in blue are sequential, clocked by the 50 MHz input clock and initialized/cleared by the common reset input. The reset is assimilated to the ''CLEAR'' command.
 [[Fișier: calc.png]]
@@ Linia 17: / Linia 17: @@
 * For the BCD converter see Exercise 3 from Applications 4. Adapt that solution such that to convert an 8 bit binary number to a three digit BCD number.
 * For the ROM module see Exercise 1 from Applications 8, or Applications 10
-  The inputs '''bmul''', '''bsub''' and '''badd''' from the push buttons, being active 0, may be transformed to single pulse internal signals, in order to easy the FSM design:
+  The inputs '''bmul''', '''bsub''' and '''badd''' from the push buttons, being active 0, may be transformed to single pulse internal signals, in order to easy the design of CTRL:
 <syntaxhighlight lang = "verilog">
 reg  button_d; // delayed button input
@@ Linia 64: / Linia 64: @@
      endcase
 end
 </syntaxhighlight>

@@ Linia 15: / Linia 15: @@
 == Design hints ==
-# For the BCD converter see Exercise 3 from Applications 4. Adapt that solution such that to convert an 8 bit binary number to a three digit BCD number.
+* For the BCD converter see Exercise 3 from Applications 4. Adapt that solution such that to convert an 8 bit binary number to a three digit BCD number.
-# For the ROM module see Exercise 1 from Applications 8, or Applications 10
+* For the ROM module see Exercise 1 from Applications 8, or Applications 10
-# The inputs '''bmul''', '''bsub''' and '''badd''' from the push buttons, being active 0, may be transformed to single pulse internal signals, in order to easy the FSM design:
+ The inputs '''bmul''', '''bsub''' and '''badd''' from the push buttons, being active 0, may be transformed to single pulse internal signals, in order to easy the FSM design:
 <syntaxhighlight lang = "verilog">
 reg  button_d; // delayed button input
@@ Linia 24: / Linia 24: @@
      button_d = button;
 assign button_p = button & ~button_d; // one clock cycle pulse generated after the push button was released
 </syntaxhighlight>