Applications 2 - Revizia istoricului

Zhascsi: /* Exercise 1 : 1 bit adder */

2025-04-02T13:29:54Z

Exercise 1 : 1 bit adder

Zhascsi: /* Module description */

2025-04-02T13:29:22Z

Module description

Zhascsi: /* Module declaration */

2025-04-02T13:29:09Z

Module declaration

Zhascsi la 2 aprilie 2025 13:28

2025-04-02T13:28:52Z

Zhascsi: /* Exercise 4 */

2023-03-12T12:11:08Z

Exercise 4

Zhascsi: /* Exercise 4 */

2023-03-08T00:58:23Z

Exercise 4

Zhascsi: /* Implementation */

2023-03-08T00:50:13Z

Implementation

Zhascsi: /* Implementation */

2023-03-08T00:47:14Z

Implementation

Zhascsi: /* simulation module */

2023-03-08T00:43:52Z

simulation module

Zhascsi: /* simulation module */

2023-03-08T00:43:05Z

simulation module

@@ Linia 17: / Linia 17: @@
 <syntaxhighlight lang="SystemVerilog">
 module adder (            // keyword '''module''' followed by the module's name and the opening parenthesis of the interface
-     input  logic a,        // one-bit input port named 'a'
+     input  logic a,       // one-bit input port named 'a'
-     input  logic b,        // one-bit input port named 'b'
+     input  logic b,       // one-bit input port named 'b'
      output logic [1:0] s  // two-bit output port. Bit 1 is MSB, bit 0 is LSB. There is no comma after the last port declaration
 );                        // the closing parenthesis of the interface and the semicolon that ends the module's declaration
@@ Linia 91: / Linia 91: @@
 <syntaxhighlight lang="SystemVerilog">
-logic num1;           // one-bit variable of type reg and named 'num1'
+logic num1;          // one-bit variable of type reg and named 'num1'
-logic num2;           // one-bit variable of type reg and named 'num2'
+logic num2;          // one-bit variable of type reg and named 'num2'
 logic [1:0] result;  // two-bit variable of type wire and named 'result'
 </syntaxhighlight>

@@ Linia 41: / Linia 41: @@
 <syntaxhighlight lang="SystemVerilog">
 module adder (
-     input logic a,
+     input  logic a,
-     input logic b,
+     input  logic b,
      output logic [1:0] s
 );
@@ Linia 50: / Linia 50: @@
 endmodule
 </syntaxhighlight>
-−
 ==== Testbench module ====

@@ Linia 17: / Linia 17: @@
 <syntaxhighlight lang="SystemVerilog">
 module adder (            // keyword '''module''' followed by the module's name and the opening parenthesis of the interface
-     input logic a,        // one-bit input port named 'a'
+     input  logic a,        // one-bit input port named 'a'
-     input logic b,        // one-bit input port named 'b'
+     input  logic b,        // one-bit input port named 'b'
      output logic [1:0] s  // two-bit output port. Bit 1 is MSB, bit 0 is LSB. There is no comma after the last port declaration
 );                        // the closing parenthesis of the interface and the semicolon that ends the module's declaration

@@ Linia 15: / Linia 15: @@
 The module declaration comprises the keyword '''module''', the module name and its interface, and ends with a semicolon:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
-module adder (      // keyword '''module''' followed by the module's name and the opening parenthesis of the interface
+module adder (            // keyword '''module''' followed by the module's name and the opening parenthesis of the interface
-     input a,        // one-bit input port named 'a'
+     input logic a,        // one-bit input port named 'a'
-     input b,        // one-bit input port named 'b'
+     input logic b,        // one-bit input port named 'b'
-     output [1:0] s  // two-bit output port. Bit 1 is MSB, bit 0 is LSB. There is no comma after the last port declaration
+     output logic [1:0] s  // two-bit output port. Bit 1 is MSB, bit 0 is LSB. There is no comma after the last port declaration
-);                  // the closing parenthesis of the interface and the semicolon that ends the module's declaration
+);                        // the closing parenthesis of the interface and the semicolon that ends the module's declaration
 </syntaxhighlight>
 ==== Module description ====
@@ Linia 34: / Linia 31: @@
 The one-bit adder may be described by a simple expression that computes the output value as the addition of its inputs:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 assign s = a + b; // variable value s is always equal to the sum of a and b
 </syntaxhighlight>
@@ Linia 42: / Linia 39: @@
 The full code of the ''adder'' module:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module adder (
-     input a,
+     input logic a,
-     input b,
+     input logic b,
-     output [1:0] s
+     output logic [1:0] s
 );
@@ Linia 80: / Linia 77: @@
 The ''adder'' module is instantiated with the name ''dut''. Its inputs receive signals ''num1'' and ''num2'', and its output is connected to a wire named ''result'':
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 adder dut (        // a module of type 'adder' is instantiated. The name of this instance is 'dut'
      .a  (num1  ),  // port 'a' is connected to signal 'num1'
@@ Linia 93: / Linia 90: @@
 For the multi-bit signals the declaration must specify the width, in the same way you declare the width of a multi-bit port in the interface of a module.
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
-reg num1;           // one-bit variable of type reg and named 'num1'
+logic num1;           // one-bit variable of type reg and named 'num1'
-reg num2;           // one-bit variable of type reg and named 'num2'
+logic num2;           // one-bit variable of type reg and named 'num2'
-wire [1:0] result;  // two-bit variable of type wire and named 'result'
+logic [1:0] result;  // two-bit variable of type wire and named 'result'
 </syntaxhighlight>
@@ Linia 103: / Linia 100: @@
 The stimuli for the ''adder'' block are generated as in Laboratory 1, using a Verilog '''initial''' block, inside which you assign values to signals ''num1'' and ''num2''. To thoroughly test the ''adder'' block it is useful to generate all possible combinations of values for those two signals. One such sequence of binary value pairs may be ''00'', ''01'', ''10'', ''11'':
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial begin
         num1 = 1'b0; num2 = 1'b0; // begin with both adder inputs zero
@@ Linia 117: / Linia 114: @@
 The full code of the ''adder'' testbench module:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module adder_tb;
 // declarations
-reg num1;
+logic num1;
-reg num2;
+logic num2;
-wire [1:0] result;
+logic [1:0] result;
 // instantion
@@ Linia 157: / Linia 154: @@
 Since the description is high-level, employing the add operator, it is exactly the same as for the previous adder.
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module adder2 (
-     input  [1:0] a,
+     input  logic [1:0] a,
-     input  [1:0] b,
+     input  logic [1:0] b,
-     output [2:0] s
+     output logic [2:0] s
 );
@@ Linia 174: / Linia 171: @@
 If the combinations are generated in a systematic way (for example in the increasing order of the input values), a '''for''' statement is more convenient.
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module adder2_tb;
 // declarations
-reg  [1:0] num1;
+logic [1:0] num1;
-reg  [1:0] num2;
+logic [1:0] num2;
-wire [2:0] result;
+logic [2:0] result;
 // instantion of a 2 bit adder
@@ Linia 190: / Linia 187: @@
 // stimuli generation
-integer i; // integer type variable used to control the for loop
+int i; // integer type variable used to control the for loop
 initial begin
      {num1, num2} = 0;                       // initial values of the adder2 inputs

@@ Linia 240: / Linia 240: @@
 The whole circuit has a multilevel hierarchy with mixed description: the top-level has a ''structural description'', while the low-level blocks have ''behavioral descriptions''.
-'''Note:''' If two or more instances of the same module appear inside another module desciption, they should have distinct instance names. Each instance should be uniquely identified.
+'''Note:''' If two or more instances of the same module appear inside another module description, they should have distinct instance names. Each instance should be uniquely identified.
 '''Note:''' The structural description has instances and wires that connect the instances between them and to the ports.
 [[Fișier: app2_multsum.png]]
 Write a testbench source file for the top-level entity.

@@ Linia 237: / Linia 237: @@
 === Exercise 4 ===
-design source file for top-level entity
+Design a source file for top-level entity. It instantiates two 1 bit adder modules (desined in Exercise 1) and one multiplier module from Exercise 3.
-Multilevel hierarchy. Mixed description: top-level - structural description, low-level - behavioral description.
+The whole circuit has a multilevel hierarchy with mixed description: the top-level has a ''structural description'', while the low-level blocks have ''behavioral descriptions''.
-* same module type, different instance names
-* internal wires for interinstance connections
+'''Note:''' If two or more instances of the same module appear inside another module desciption, they should have distinct instance names. Each instance should be uniquely identified.
 [[Fișier: app2_multsum.png]]
-testbench source file for the top-level entity
+Write a testbench source file for the top-level entity.

@@ Linia 206: / Linia 206: @@
 <syntaxhighlight>
-set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { num1 }];
+set_property -dict { PACKAGE_PIN T2   IOSTANDARD LVCMOS33 } [get_ports { a[1] }];
 </syntaxhighlight>
-is a constraint that connects the port num1 to the FPGA pin labelled M20.
+is a constraint that connects the first bit of a input to the FPGA pin labelled T2.
-Hopefully, for each FPGA board you may find constraints files with constraints for all FPGA pins, with indications as to which switch, button, LED, a.s.o. is connected to which FPGA pin. All constraints are commented. You should uncomment only the lines for the switches, buttons, LEDs a.s.o. that you want to use, and replace the port names with the names of ports from your module. For multi-bit ports there must be one separate connection constraint for each port bit, since each port bit needs a separate FPGA pin.
+'''Note:''' For each FPGA board you may find constraints files with constraints for all FPGA pins, with indications as to which switch, button, LED, a.s.o. is connected to which FPGA pin. All constraints are commented. You should uncomment only the lines for the switches, buttons, LEDs a.s.o. that you want to use, and replace the port names with the names of ports from your module. For multi-bit ports there must be one separate connection constraint for each port bit, since each port bit needs a separate FPGA pin.
 The 2 bit adder will be tested using four switches to set the input values, and three LEDs to show the output 3-bit value:

@@ Linia 219: / Linia 219: @@
 <syntaxhighlight>
 ##Switches
-set_property -dict { PACKAGE_PIN M20   IOSTANDARD LVCMOS33 } [get_ports { a }]; #SW 0
+set_property -dict { PACKAGE_PIN T2   IOSTANDARD LVCMOS33 } [get_ports { a[1] }]; #SW 3
-set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { b }]; #SW 1
+set_property -dict { PACKAGE_PIN U1   IOSTANDARD LVCMOS33 } [get_ports { a[0] }]; #SW 2
 ##LEDs
-set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { s[0] }]; #LED 0
+set_property -dict { PACKAGE_PIN G1   IOSTANDARD LVCMOS33 } [get_ports { s[0] }]; #LED 0
-set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { s[1] }]; #LED 1
+set_property -dict { PACKAGE_PIN G2   IOSTANDARD LVCMOS33 } [get_ports { s[1] }]; #LED 1
 </syntaxhighlight>

@@ Linia 172: / Linia 172: @@
 The 2 bit adder module has two inputs of 2 bits each. That means there are more input combinations to be tested, actually 16 (4 values for the one input, and 4 values for the other one). To run through all those 16 combinations the pair of statements '''num1 ='''''value1''; '''num2 ='''''value2''; may be employed 16 times with different values.
-If the combinations are generated in a systematic way (for example in the increasing order of the input values), a for statement is more convenient.
+If the combinations are generated in a systematic way (for example in the increasing order of the input values), a '''for''' statement is more convenient.
 <syntaxhighlight lang="Verilog">

@@ Linia 171: / Linia 171: @@
 ==== simulation module ====
-The 2 bit adder module has two inputs of 2 bits each. That means there are more input combinations to be tested, actually 16 (4 values for the one input, and 4 values for the other one). To run through all those 16 combinations the pair of statements ''''num1 =''''''value1''; ''''num2 =''''''value2''; may be employed 16 times with different values.
+The 2 bit adder module has two inputs of 2 bits each. That means there are more input combinations to be tested, actually 16 (4 values for the one input, and 4 values for the other one). To run through all those 16 combinations the pair of statements '''num1 ='''''value1''; '''num2 ='''''value2''; may be employed 16 times with different values.
 If the combinations are generated in a systematic way (for example in the increasing order of the input values), a for statement is more convenient.