Applications 3 - Revizia istoricului

Zhascsi: /* 2 to 1 multiplexer, structural description: gate-level */

2025-04-02T13:35:05Z

2 to 1 multiplexer, structural description: gate-level

2025-02-22T18:02:56Z

2 to 1 multiplexer, behavioral description

2025-02-22T18:02:04Z

2 to 1 multiplexer, behavioral description

2025-02-22T17:58:43Z

4 to 1 multiplexer, behavioral description

2025-02-22T17:58:03Z

2 to 1 multiplexer, alternative behavioral description

2025-02-22T17:57:08Z

2 to 1 multiplexer, behavioral description

2023-03-13T10:00:53Z

4 to 1 multiplexer, structural description

2023-03-13T09:46:39Z

4 to 1 multiplexer, behavioral description

2023-03-13T02:10:13Z

2023-03-13T02:08:20Z

for statement

@@ Linia 136: / Linia 136: @@
 [[Fișier: Mux2a.png]]
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module mux2(
-     input s,
+     input  logic s,
-     input [1:0] in,
+     input  logic [1:0] in,
-     output y
+     output logic y
 );
-wire s_n;
+logic s_n;
-wire w1;
+logic w1;
-wire w0;
+logic w0;
 // gate-level structural description
@@ Linia 155: / Linia 155: @@
 endmodule
 </syntaxhighlight>
 === 2 to 1 multiplexer, FPGA implementation ===

@@ Linia 64: / Linia 64: @@
 The statements employed may be assignments, conditional assignments and procedural statements ('''if''', '''case''').
-The '''always''' block of statements is executed whenever any of the variables inside the blocks RHS assignments changes its value. The statements are executed in the exact order in which they appear inside the '''always''' block.
+The '''always''' block of statements is executed whenever any of the variables inside the block's RHS assignments changes its value. The statements are executed in the exact order in which they appear inside the '''always''' block.
 <syntaxhighlight lang="SystemVerilog">

@@ Linia 57: / Linia 57: @@
 === 2 to 1 multiplexer, behavioral description ===
-Uses one or more '''always''' blocks. The template of an '''always''' block is:
+Uses one or more '''always''' blocks. The template of an '''always''' block that describes a combinational logic circuit is:
-'''always @('''''sensitivity list''''') begin'''<br />
+'''always_comb begin'''<br />
 &nbsp;&nbsp;''block of statements''<br />
 '''end'''
 The statements employed may be assignments, conditional assignments and procedural statements ('''if''', '''case''').
-The '''always''' block of statements is executed whenever any of the variables from the sensitivity list changes its value. The statements are executed in the exact order in which they appear inside the '''always''' block.
+The '''always''' block of statements is executed whenever any of the variables inside the blocks RHS assignments changes its value. The statements are executed in the exact order in which they appear inside the '''always''' block.
 <syntaxhighlight lang="SystemVerilog">
@@ Linia 86: / Linia 84: @@
 </syntaxhighlight>
 '''Note:''' Bit selection operator ('''[ ]''') is used to select a bit (or a couple of consecutive bits) from a multibit variable. '''in[0]''' is bit 0 from the input vector '''in'''.

@@ Linia 323: / Linia 323: @@
 ''value1'', ''value2'' a.s.o. are integer values of the ''selectVariable''
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
-always @(*) begin
+always_comb begin
      case(s)
 : y = in[0];

@@ Linia 97: / Linia 97: @@
 The codes below show three alternative behavioral descriptions for the above multiplexer:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 // behavioral description with case
-always @(*) begin
+always_comb begin
      case(s)
 : y = in[0];
@@ Linia 108: / Linia 108: @@
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 // behavioral description with conditional assignment
-always @(*) begin
+always_comb begin
      y = s ? in[1] : in[0];
 end
@@ Linia 116: / Linia 116: @@
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 // behavioral description with vector selection
-always @(*) begin
+always_comb begin
      y = in[s];
 end
@@ Linia 124: / Linia 124: @@
 '''Note:''' The last two alternatives may be also employed in continuous assignments, because they are single statements. For example vector selection may be used inside an '''assign''' instead of an '''always''': <syntaxhighlight lang="Verilog" inline>assign y = in[s];</syntaxhighlight>.
 === 2 to 1 multiplexer, structural description: gate-level ===

@@ Linia 347: / Linia 347: @@
 [[Fișier: mux4b.png]]
-Implement the 4 to 1 multiplexer using three instances of the 2 to 1 multiplexer (add to the project one of the design source files from Exercise 1).
+Design the 4 to 1 multiplexer using three instances of the 2 to 1 multiplexer (from Exercise 1).
 Be careful to distinctly name each instance and each internal wire!

@@ Linia 326: / Linia 326: @@
 <syntaxhighlight lang="Verilog">
-case(s)
+always @(*) begin
-: y = in[0];
+    case(s)
-: y = in[1];
+: y = in[0];
-: y = in[2];
+: y = in[1];
-: y = in[3];
+: y = in[2];
-endcase
+: y = in[3];
 </syntaxhighlight>
 '''Note:''' As in Exercise 1, a much more compact description is possible with bit selection, <syntaxhighlight lang="Verilog" inline>assign y = in[s];</syntaxhighlight>.
 == Exercise 5 ==

@@ Linia 246: / Linia 246: @@
 end
 </syntaxhighlight>
 === repeat statement ===
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 This table may be read either as the addition table, with '''s''' considered as a base-2 number value, or it may be read as a truth table, if '''s''' is viewed as a pair of two logic values. Each bit of '''s''' may be computed as a logic function with two arguments.
 === half adder, data-flow description ===

@@ Linia 237: / Linia 237: @@
 <syntaxhighlight lang="Verilog">
-integer index
+integer index;
 initial begin
      {s, a, b} = 0;
@@ Linia 246: / Linia 246: @@
 end
 </syntaxhighlight>
 === repeat statement ===