Applications 4 - Revizia istoricului

Zhascsi: /* top design module */

2025-04-02T13:30:59Z

top design module

Zhascsi: /* transcoder */

2025-04-02T13:30:34Z

transcoder

Zhascsi: /* transcoder */

2025-02-22T22:40:33Z

transcoder

Zhascsi: /* top design module */

2023-03-27T11:09:07Z

top design module

Zhascsi la 21 martie 2023 23:43

2023-03-21T23:43:56Z

Afișare diferențe

Zhascsi la 20 martie 2023 09:28

2023-03-20T09:28:02Z

Zhascsi la 18 aprilie 2022 06:29

2022-04-18T06:29:33Z

Zhascsi la 21 martie 2022 00:45

2022-03-21T00:45:09Z

Zhascsi: /* Testbench */

2022-03-21T00:23:19Z

Testbench

Zhascsi la 21 martie 2022 00:20

2022-03-21T00:20:14Z

@@ Linia 56: / Linia 56: @@
 <syntaxhighlight lang="Verilog">
 module top(
-     input  [3:0] num,
+     input  logic [3:0] num,
-     output [6:0] seg,
+     output logic [6:0] seg,
-     output [7:0] anode
+     output logic [7:0] anode
 );

@@ Linia 25: / Linia 25: @@
 <syntaxhighlight lang="SystemVerilog">
 module transcoder(
-     input      [3:0] value,
+     input  logic [3:0] value,
-     output reg [6:0] seg
+     output logic [6:0] seg
 );

@@ Linia 23: / Linia 23: @@
 |}
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 module transcoder(
      input      [3:0] value,
@@ Linia 29: / Linia 29: @@
 );
-always @(*) begin
+always_comb begin
      case (value)
 'd0:    seg = 7'b1000000;

@@ Linia 62: / Linia 62: @@
 transcoder transcoder(
-     .value (num)
+     .value (num),
      .seg   (seg)
 );
@@ Linia 70: / Linia 70: @@
 endmodule
 </syntaxhighlight>
 === implementation ===

@@ Linia 89: / Linia 89: @@
 | <syntaxhighlight lang="Verilog" inline>8'b00000011</syntaxhighlight> || 3, in binary format on 8 bits. Leading zeros are explicitly written
 |-
-| <syntaxhighlight lang="Verilog" inline>8'b0000_0011</syntaxhighlight> || when there are too many bits, the underline, '''_''' may be used to split bits into smaller groups
+| <syntaxhighlight lang="Verilog" inline>8'b0000_0011</syntaxhighlight> || when there are many bits, the underline, '''_''', may be used to split bits into smaller groups that are easier to read
 |}
 <!--
 Open the ''transcoder'' VPL activity on Moodle, upload the source file of the transcoder, run the test and check the results. In case of errors fix the design and retry. After you get TEST PASS on Moodle, proceed to implementation.
-Test the transcoder by connecting its 4 bit input to BTN[3], BTN[2], BTN[1] and BTN[0], and displaying the output on a 7-segment display, the right digit (Digit0) of PMOD-SSD <!--(DE1-SOC for)--> display.
+Test the transcoder by connecting its 4 bit input to BTN[3], BTN[2], BTN[1] and BTN[0], and displaying the output on a 7-segment display, the right digit (Digit0) of PMOD-SSD <!--(DE1-SOC for) display.-->
 '''Coding style:'''
@@ Linia 103: / Linia 123: @@
 [[Fișier: letters.png]]
-<!--
 == Exercise 3 ==
@@ Linia 110: / Linia 131: @@
 [[Fișier: app4_adder.png]]
-The result of the 3 bit addition is in the range [0, ... ,14] and it may be written in the hexadecimal base using only one digit.
+The result of the 3 bit addition is an integer in the range [0 ... 14], and it may be written in the hexadecimal base using only one digit.
-The transcoder must be extended to show hexadecimal digits greater than 9. Use the most common 7-segment symbols for them:
+The transcoder must be extended to show all hexadecimal digits, including those greater than 9.
 # create a new project in a new folder

@@ Linia 69: / Linia 69: @@
 To display the ASCII values on the waveforms in simulation, right-click the name of the variable in the Simulation panel and select from the pop-up menu '''radix''' -> '''ASCII'''
-<!--
-== <span id="transcoder">Exercise 1</span> ==
+== <span id="transcoder">Exercise 2</span> ==
 Make a 7-segment display transcoder using a '''case''' block that displays values from 0 to 9. The input of the module will be called '''value''' and the output '''seg'''.
@@ Linia 91: / Linia 91: @@
 | <syntaxhighlight lang="Verilog" inline>8'b0000_0011</syntaxhighlight> || when there are too many bits, the underline, '''_''' may be used to split bits into smaller groups
 |}
+<!--
 Open the ''transcoder'' VPL activity on Moodle, upload the source file of the transcoder, run the test and check the results. In case of errors fix the design and retry. After you get TEST PASS on Moodle, proceed to implementation.
-Test the transcoder by connecting its 4 bit input to SW[3], SW[2], SW[1] and SW[0], and displaying the output on a 7-segment display, the right digit (Digit0) of DE1-SOC display.
+Test the transcoder by connecting its 4 bit input to BTN[3], BTN[2], BTN[1] and BTN[0], and displaying the output on a 7-segment display, the right digit (Digit0) of PMOD-SSD <!--(DE1-SOC for)--> display.
 '''Coding style:'''
 * '''case''' statements should always include the '''default''' case.
-== Exercise 2 ==
+The transcoder may be extended to show hexadecimal digits greater than 9. Use the most common 7-segment symbols for them:
 Implement a 3 bit adder whose result is displayed as a hexadecimal digit.

@@ Linia 3: / Linia 3: @@
 The Caesar cipher is the simplest substitution cipher. A plain text message is encrypted by replacing each letter from the message by another one that is some fixed number of positions down the alphabet. All letters of the alphabet are changed using the same fixed number of positions. The letters are “shifted” down the alphabet, this code being also named shift cipher.
-In this exercise and the following ones, we assume that the plain and encoded messages contain only ASCII uppercase letters A to Z, without blank spaces between words. The encryption is done such that A-Z set of letters are translated to letters from the same set A-Z. For example, if the shift is of 3 positions down the alphabet, ''A'' translates to ''D'', ''B'' to ''E'', ''C'' to ''F'', a.s.o. To achieve the circularity of the encoding, ''W'' translates to ''Z'', ''X'' to ''A'', ''Y'' to ''B'' and ''Z'' to ''C''.
+In this exercise and the following ones, we assume that the plain and encoded messages contain only ASCII uppercase letters A to Z, without blank spaces between words. The encryption is done such that A-Z set of letters are translated to letters from the same set A-Z. For example, if the shift is of 3 positions down the alphabet, '''A''' translates to '''D''', '''B''' to '''E''', '''C''' to '''F''', a.s.o. To achieve the circularity of the encoding, '''W''' translates to '''Z''', '''X''' to '''A''', '''Y''' to '''B''' and '''Z''' to '''C'''.
 [[Fișier: Dic_lab4_cipher_shift.png]]
@@ Linia 69: / Linia 69: @@
 To display the ASCII values on the waveforms in simulation, right-click the name of the variable in the Simulation panel and select from the pop-up menu '''radix''' -> '''ASCII'''
 == <span id="transcoder">Exercise 1</span> ==
@@ Linia 136: / Linia 137: @@
 # assign switches SW[9], SW[8] and SW[7] for the input a, SW[2], SW[1] and SW[0] for the input b, Digit0 pins for seg0, and Digit1 pins for seg1
 # implement and check that the result of multiplying two 3 bit numbers is correctly displayed on two digits in decimal format. If the result is smaller than ten, the first digit will show a leading 0)

@@ Linia 38: / Linia 38: @@
 The testbench instantiates two Caesar encoder modules. The first one is the encoder itself, that generates the encoded message. The second instance uses the reversed shift to decode the encrypted message. The shift value (for example 13) may be assigned directly to the shift port of the instance as a literal constant:
 <syntaxhighlight lang="Verilog">
-module caesar encoder (
+caesar encoder (
      .shift (8'd13),
      // other port connections
 );
 </syntaxhighlight>
 The testbench generates a sequence of ASCII values for the data_sent input of the encoder. The verilog language allows you to assign to an 8-bit logic variable an ASCII value as a character: