Applications 6 - Revizia istoricului

Zhascsi: /* clock generation in testbench */

2025-02-22T17:07:48Z

clock generation in testbench

Zhascsi: /* Exercise 1 */

2019-04-07T16:14:05Z

Exercise 1

Zhascsi la 4 aprilie 2019 05:30

2019-04-04T05:30:54Z

Zhascsi la 4 aprilie 2019 05:14

2019-04-04T05:14:20Z

Zhascsi: /* Exercise 1 */

2019-04-04T05:12:33Z

Exercise 1

Zhascsi: /* the shift operator */

2019-04-03T21:12:19Z

the shift operator

Zhascsi la 3 aprilie 2019 21:10

2019-04-03T21:10:23Z

Zhascsi: /* clock generation in testbench */

2019-04-03T10:57:31Z

clock generation in testbench

Zhascsi la 3 aprilie 2019 07:35

2019-04-03T07:35:31Z

Zhascsi: Pagină nouă: == Exercise 1 == === D flip-flop === Fișier: dreg1.png the output takes the value of the input, q <= d, but only at...

2019-04-02T21:58:25Z

Pagină nouă: == Exercise 1 == === D flip-flop === Fișier: dreg1.png the output takes the value of the input, <syntaxhighlight lang="Verilog" inline>q <= d</syntaxhighlight>, but only at...

Pagină nouă

== Exercise 1 ==
=== D flip-flop ===

[[Fișier: dreg1.png]]

the output takes the value of the input, <syntaxhighlight lang="Verilog" inline>q <= d</syntaxhighlight>, but only at discrete moments of time,
when the control signal '''clk''' changes from '''0''' to '''1''', <syntaxhighlight lang="Verilog" inline>always @(posedge clk)</syntaxhighlight>.

=== clock generation in testbench ===

<syntaxhighlight lang="Verilog">
initial begin
clk = 0; // initialization at time 0
forever #5 clk = ~clk; // toggle the clock at each 5 simulation steps
end
</syntaxhighlight>

== Exercise 2 ==
=== 8 bit D register ===

[[Fișier: reg8.png]]

=== structural description with flip-flops ===

[[Fișier: reg4.png]]

← Versiunea anterioară		Versiunea de la data 7 aprilie 2019 16:14
Linia 35:		Linia 35:
	See how the output '''q''' reacts or not to changes of the input '''d'''.		See how the output '''q''' reacts or not to changes of the input '''d'''.

		+	'''Attention!'''
		+	* the stimuli are generated in other initial processes, separate from the initial process that is used only for clock generation (which loops forever, and cannot go beyond the '''forever''' statement)
		+	* because the clock is continuously generated, the simulation doesn't stop by itself. It may be stopped from simulation menu buttons (the red stop button or the break button). A more practical approach (that restricts from the beginning the waveform to the area of interest) is to stop the simulation from the testbench through the <syntaxhighlight lang="Verilog" inline>$stop</syntaxhighlight> sistem task added with a convenient delay after the last stimulus change:
		+
		+	<syntaxhighlight lang="Verilog">
		+	initial begin
		+	// code to generate various stimuli (data, control signals etc)
		+	#10 $stop;
		+	end
		+	</syntaxhighlight>

	== Exercise 2 ==		== Exercise 2 ==

@@ Linia 50: / Linia 50: @@
 [[Fișier: reg4wave.png]]
 === structural description with flip-flops ===
@@ Linia 105: / Linia 106: @@
 <syntaxhighlight lang="Verilog">
-always @(posedge clk, posedge rst) begin
+always @(posedge clk, posedge rst) begin // the reset signal appears in the sensitivity list, therefore the always process reacts immediately to it
      if(rst) begin
          // initialize sequential variables
@@ Linia 116: / Linia 117: @@
 * change the '''dff1''' description such that it reacts to an asynchronous reset which is active low, recompile, restart simulation and see how the output waveform is affected
+* shorten the length of the reset pulse, such that there is no any active clock edge during the reset as in the waveform below. Rerun and see that the asynchronous reset takes effect.
 === nonblocking versus blocking assignments ===

@@ Linia 34: / Linia 34: @@
 See how the output '''q''' reacts or not to changes of the input '''d'''.
 == Exercise 2 ==
@@ Linia 57: / Linia 58: @@
 [[Fișier: reg4.png]]
 == Exercise 3 ==
@@ Linia 66: / Linia 68: @@
 [[Fișier: shiftr4.png]]
 === reset ===
@@ Linia 114: / Linia 117: @@
 * change the '''dff1''' description such that it reacts to an asynchronous reset which is active low, recompile, restart simulation and see how the output waveform is affected
 === nonblocking versus blocking assignments ===
@@ Linia 133: / Linia 137: @@
      q[0]  = q[1]
 </syntaxhighlight>
 === a simpler behavioral description ===

@@ Linia 14: / Linia 14: @@
 * any sequential variable is of '''reg''' type
 * all assignments for sequential variables are '''nonblocking assignments''', i.e. they use the <syntaxhighlight lang="Verilog" inline><=</syntaxhighlight> operator
 === clock generation in testbench ===
@@ Linia 23: / Linia 24: @@
 end
 </syntaxhighlight>
 For the '''d''' input generate the following sequence in testbench:

@@ Linia 129: / Linia 129: @@
 </syntaxhighlight>
-=== the shift operator ===
+=== a simpler behavioral description ===
 * change the '''shiftr4''' behavioral description such that all bits are shifted at once in a single statement that uses the concatenation operator:
 <syntaxhighlight lang="Verilog">q <= {si,q[3:1]} // the new value is the old value shifted one bit to the right and with si bit appended to its left</syntaxhighlight>

@@ Linia 18: / Linia 18: @@
 === clock generation in testbench ===
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial begin
      clk = 0;                 // initialization at time 0
@@ Linia 39: / Linia 41: @@
 * because the clock is continuously generated, the simulation doesn't stop by itself. It may be stopped from simulation menu buttons (the red stop button or the break button). A more practical approach (that restricts from the beginning the waveform to the area of interest) is to stop the simulation from the testbench through the <syntaxhighlight lang="Verilog" inline>$stop</syntaxhighlight> sistem task added with a convenient delay after the last stimulus change:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial begin
      // code to generate various stimuli (data, control signals etc)

@@ Linia 2: / Linia 2: @@
 === D flip-flop ===
-* '''dff''' module with behavioral description of the D flip-flop
+* '''dff1''' module with behavioral description of the D flip-flop
-* '''dff_tb''' testbench with stimuli for '''d''' and '''clk'''
+* '''dff1_tb''' testbench with stimuli for '''d''' and '''clk'''
 [[Fișier: dreg1.png]]
@@ Linia 47: / Linia 47: @@
 === structural description with flip-flops ===
-* add '''dff''' file to this project
+* add '''dff1''' file to this project
-* change the description of '''reg4''' to a structural one, with 4 instances of '''dff''', connected as in the schematics below:
+* change the description of '''reg4''' to a structural one, with 4 instances of '''dff1''', connected as in the schematics below:
 * rerun the testbench
@@ Linia 57: / Linia 57: @@
 * '''shiftr4''' module described structurally as in the schematics below. It is basically the '''reg4''' module, but with the D flip-flops connected in a shift chain.
-* '''dff''' is added (copied) to this project
+* '''dff1''' is added (copied) to this project
 * '''shiftr4_tb''' testbench with '''clk''' generation and a (random) bit sequence for '''si''' (serial input)
@@ Linia 72: / Linia 72: @@
 [[Fișier: shiftr4rst.png]]
 For any sequential process with reset (active '''1''' in the examples below) the template is:
@@ Linia 101: / Linia 107: @@
 </syntaxhighlight>
-=== behavioral description ===
+* change the '''dff1''' description such that it reacts to an asynchronous reset which is active low, recompile, restart simulation and see how the output waveform is affected
-−
 === nonblocking versus blocking assignments ===
 * compare in simulation these two behavioral descriptions of the '''shiftr4''' module:
 <syntaxhighlight lang="Verilog">
      q[3] <= si
@@ Linia 116: / Linia 121: @@
      q[0] <= q[1]
 </syntaxhighlight>
+# the wrong description with blocking assignments
 <syntaxhighlight lang="Verilog">
      q[3]  = si
@@ Linia 123: / Linia 128: @@
      q[0]  = q[1]
 </syntaxhighlight>

@@ Linia 1: / Linia 1: @@
 == Exercise 1 ==
 === D flip-flop ===
 [[Fișier: dreg1.png]]
@@ Linia 6: / Linia 9: @@
 the output takes the value of the input, <syntaxhighlight lang="Verilog" inline>q <= d</syntaxhighlight>, but only at discrete moments of time,
 when the control signal '''clk''' changes from '''0''' to '''1''', <syntaxhighlight lang="Verilog" inline>always @(posedge clk)</syntaxhighlight>.
 === clock generation in testbench ===
@@ Linia 12: / Linia 20: @@
 initial begin
      clk = 0;                // initialization at time 0
-     forever #5 clk = ~clk;  // toggle the clock at each 5 simulation steps
+     forever #10 clk = ~clk;  // toggle the clock at each 10 simulation steps
 end
 </syntaxhighlight>
 == Exercise 2 ==
-=== 8 bit D register ===
+=== 4 bit D register ===
 [[Fișier: reg8.png]]
 === structural description with flip-flops ===
 [[Fișier: reg4.png]]