Applications 7 - Revizia istoricului

Zhascsi: /* 32 bit Counter : Synchronous load */

2025-04-13T15:15:05Z

32 bit Counter : Synchronous load

Zhascsi: /* 32 bit Counter : Synchronous load */

2025-04-13T12:18:35Z

32 bit Counter : Synchronous load

Zhascsi: /* 32 bit Counter : Count enable */

2025-04-13T12:15:11Z

32 bit Counter : Count enable

Zhascsi: /* 32 bit Counter : Reset */

2025-04-13T12:12:21Z

32 bit Counter : Reset

Zhascsi: /* 32 bit Counter : Count enable */

2025-04-13T12:08:14Z

32 bit Counter : Count enable

Zhascsi: /* 32 bit Counter : Behavioral description */

2025-04-13T12:07:01Z

32 bit Counter : Behavioral description

Zhascsi: /* 32 bit Counter : Behavioral description */

2025-04-13T11:32:34Z

32 bit Counter : Behavioral description

Zhascsi: /* 32 bit Counter : Behavioral description */

2025-04-13T11:23:33Z

32 bit Counter : Behavioral description

Zhascsi: /* 32 bit Counter : Synchronous load */

2019-04-10T19:10:45Z

32 bit Counter : Synchronous load

Zhascsi: /* 32 bit Counter : Synchronous load */

2019-04-10T19:09:24Z

32 bit Counter : Synchronous load

@@ Linia 110: / Linia 110: @@
 |}
-The X in the first row means that the value of '''ce''' input doesn't matter (it may be either '''0''' or '''1''') because '''ld''' has priority over '''ce'''. The truth table can thus be substantially compressed. Instead of two separate rows for the input combinations ('''ld'''='''0''', '''ce'''='''0''') and ('''ld'''='''0''', '''ce'''='''1'''), for which the function is the same (load), a single combintion is used ('''ld'''='''0''', '''ce'''='''X''').
+The X in the first row means that the value of '''ce''' input doesn't matter (it may be either '''0''' or '''1''') because '''ld''' has priority over '''ce'''. The truth table can thus be substantially compressed. Instead of two separate rows for the input combinations ('''ld'''='''1''', '''ce'''='''0''') and ('''ld'''='''1''', '''ce'''='''1'''), for which the function is the same (load), a single combination is used ('''ld'''='''1''', '''ce'''='''X''').
 This compaction can also be used in Verilog table constructions, such as the 'case' statement. In order to use the X value in specifying the cases of the instruction, the alternative '''casex''' statement, which has the same format as the '''case''' statement, must be used:
@@ Linia 144: / Linia 144: @@
 * add an '''initial''' process in the testbench to load a particular target value after some time. Try to reproduce the stimuli scenario from the figure below and see if you get the same output as in the figure:
-[[File: appl7_cnt_32_load_wave.png]]
+[[File: Lab7_cnt_32_load_wave.png]]

@@ Linia 95: / Linia 95: @@
 Another very useful feature is to bring the counter state to whatever desired value ('''target''' value). This feature makes easy the design of frequency dividers and lots of counter based automata.
-[[File: appl7_cnt_32_load.png]]
+[[File: Zlab7_cnt_32_load.png]]
 When load input ('''ld''') is active, the active clock edge causes the counter to load the value of the '''target''' input. If both control inputs ('''ld''' and '''ce''') are active, the load command has priority. All functions of this counter can be arranged in a table:
@@ Linia 103: / Linia 103: @@
 | ld || ce ||next cnt value|| function
 |- bgcolor="#ddffdd" align="left"
-|0 ||X ||target ||load
+|0 ||0 ||cnt ||freeze
 |- bgcolor="#ddffdd" align="left"
-|1 ||0 ||cnt ||freeze
+|0 ||1 ||cnt+1 ||count
 |- bgcolor="#ddffdd" align="left"
-|1 ||1 ||cnt+1 ||count
+|1 ||X ||target ||load
 |}
@@ Linia 126: / Linia 126: @@
 <syntaxhighlight lang="verilog">
 casex({ld,ce})
-'b0X: out <= target;
+'b1X: out <= target;
      // other cases
 endcase
@@ Linia 135: / Linia 135: @@
 <syntaxhighlight lang="verilog">
 case({ld,ce})
-'b00,
+'b10,
-'b01: out <= target;
+'b11: out <= target;
      // other cases
 endcase

@@ Linia 72: / Linia 72: @@
 It is useful for many counter applications to be able to sometime freeze the counting. An additional control signal, counter enable ('''ce'''), enables the counting only when it's active.
-[[File: appl7_cnt_32_en.png]]
+[[File: Zlab7_cnt_32_en.png]]
 * add the '''ce''' pin to '''cnt32''' module, and change the sequential process such that the counting is enabled only if '''ce''' is 1.
@@ Linia 78: / Linia 78: @@
 <syntaxhighlight lang="SystemVerilog">
 always_ff @(posedge clk) begin
-     if(~rst) begin
+     if(rst) begin
          // initialization at reset
      end

@@ Linia 61: / Linia 61: @@
-* add the '''rst''' pin to '''cnt32''' module, and change the sequential process such that the counter is set to 0 if reset is applied. '''rst''' is synchronous and active 0.
+* add the '''rst''' pin to '''cnt32''' module, and change the sequential process such that the counter is set to 0 if reset is applied. '''rst''' is synchronous and active 1.
 * add an initial process to the testbench to apply the reset pulse for at least two clock cycles. Rerun the simulation and see the effect of the reset.
-* assign a pushbutton (KEY0) to '''rst''' input. The pushbutton pin stays at logic 1 while the button is not touched, and receives 0 if you push the button.
+* assign a pushbutton (BTN) to '''rst''' input.
 * compile and program the FPGA
-[[File: appl7_cnt_32_rst.png]]
+[[File: Zlab7 cnt 32 rst.png]]
 === 32 bit Counter : Count enable ===

@@ Linia 76: / Linia 76: @@
 * add the '''ce''' pin to '''cnt32''' module, and change the sequential process such that the counting is enabled only if '''ce''' is 1.
-<syntaxhighlight lang="verilog">
+<syntaxhighlight lang="SystemVerilog">
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
      if(~rst) begin
          // initialization at reset
@@ Linia 90: / Linia 90: @@
 * assign a switch (SW0) to '''ce''' input
 * compile and program the FPGA
 === 32 bit Counter : Synchronous load ===

@@ Linia 21: / Linia 21: @@
 * compile and program the FPGA. The red LEDs should be blinking, LED0 about once a second, LED1 twice slower, LED2 twice slower than LED1 a.s.o.
-[[File: Appl7_cnt_32_led.png]]
+[[File: Zlab7_cnt_32_led.png]]
 === 32 bit Counter : Initial state ===

@@ Linia 10: / Linia 10: @@
 As an automaton, the counter may be regarded as a register with an incrementer closing the outer loop. The behavioral description needs only a sequential '''always''' process to update the counter value, and an assignment for the next value of the counter.
-<syntaxhighlight lang="verilog">
+<syntaxhighlight lang="SystemVerilog">
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
      cnt <= cnt + 1;
 end
@@ Linia 17: / Linia 17: @@
 * create a new project
-* create a new verilog source file for '''cnt32''', and describe it as shown above
+* create a new source file for '''cnt32''', and describe it as shown above
-* assign fpga pins to connect an external clock (use CLOCK_50 clock) and LEDs to four of the output bits, as indicated below
+* assign fpga pins to connect an external clock and LEDs to four of the output bits, as indicated below
-* compile and program the FPGA. The red LEDs should be blinking, LEDR0 nearly once a second, LEDR1 twice slower, LEDR2 twice slower than LEDR1 a.s.o.
+* compile and program the FPGA. The red LEDs should be blinking, LED0 about once a second, LED1 twice slower, LED2 twice slower than LED1 a.s.o.
 [[File: appl7_cnt_32_led.png]]
 === 32 bit Counter : Initial state ===

← Versiunea anterioară		Versiunea de la data 10 aprilie 2019 19:09
Linia 142:		Linia 142:

	* change '''cnt32''' behavioral description to conform to a synchronous counter with a synchronous load.		* change '''cnt32''' behavioral description to conform to a synchronous counter with a synchronous load.
−	* add an '''initial''' process in the testbench to load a particular target value after some time	+	* add an '''initial''' process in the testbench to load a particular target value after some time. Try to reproduce the stimuli scenario from the figure below and see if you get the same output as in the figure:
		+
		+	[[File: appl7_cnt_32_load_wave.png]]