Applications 8 - Revizia istoricului

Zhascsi: /* RAM - Read-Write Memory */

2025-04-21T21:56:52Z

RAM - Read-Write Memory

Zhascsi: /* RAM - Read-Write Memory */

2025-04-21T21:42:09Z

RAM - Read-Write Memory

Zhascsi: /* Memory initialization task */

2025-04-21T21:37:22Z

Memory initialization task

Zhascsi la 21 aprilie 2025 21:36

2025-04-21T21:36:48Z

Zhascsi la 21 aprilie 2025 21:36

2025-04-21T21:36:22Z

Zhascsi la 2 mai 2022 06:03

2022-05-02T06:03:46Z

Zhascsi la 17 aprilie 2019 19:25

2019-04-17T19:25:01Z

Zhascsi: /* Memory initialization file */

2019-04-17T19:23:42Z

Memory initialization file

Zhascsi: /* Memory initialization task */

2019-04-17T19:19:02Z

Memory initialization task

Zhascsi: /* RAM - Read-Write Memory */

2019-04-17T10:57:32Z

RAM - Read-Write Memory

@@ Linia 111: / Linia 111: @@
 * Compile, program the FPGA and test the RAM. Set switches to an address and a data value, then briefly push the write enable button. The LEDs will change accordingly. Change the address and data and push again the write enable button. Change back the address switches and see if the previously written configuration reappears on LED.
-[[Fișier: appl8_ram_wave.png]]
+[[Fișier: Zlab8_ram_wave.png]]
 <!--

@@ Linia 94: / Linia 94: @@
 A synchronous memory reacts only on clock edges. The addresses are sampled at clock edges, the output changes also on clock edges, and the write is performed on clock edges too.
-[[Fișier: appl8_ram.png]]
+[[Fișier: Zlab8_ram.png]]
 The FPGA has dedicated blocks for memory implementation, the so called ''ram blocks'', or ''ramblocks''. In order for the synthesis to map a memory description to a ''ramblock'', the sequential description must conform to a template:

@@ Linia 48: / Linia 48: @@
 If the memory initialization file, ''meminit.txt'', resides in the project's folder, and the memory array to be initialized is '''mem''' inside the memory instance '''dut''', the testbench may initialize the memory right at the beginning of the simulation:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial $readmemb("../../meminit.txt", dut.mem);
 </syntaxhighlight>

@@ Linia 7: / Linia 7: @@
 <syntaxhighlight lang = "SystemVerilog">
-logic [W-1: 0] memory [0: N-1];
+logic [W-1:0] memory [0:N-1];
 </syntaxhighlight>

@@ Linia 6: / Linia 6: @@
 Being a vector of words or a bidimensional array of bits, the memory could be described using a single bidimensional variable, usually declared as a vector of multibit '''reg''' items. A memory array of N locations, with W bits per location is declared as:
-<syntaxhighlight lang = "verilog">
+<syntaxhighlight lang = "SystemVerilog">
-reg [W-1: 0] memory [0: N-1];
+logic [W-1: 0] memory [0: N-1];
 </syntaxhighlight>
 '''Attention!'''
-* the width of the word is declared as usual, with msb as the left index, <syntaxhighlight lang="Verilog" inline>[msb:0]</syntaxhighlight>
+* the width of the word is declared as usual, with msb as the left index, <syntaxhighlight lang="SystemVerilog" inline>[msb:0]</syntaxhighlight>
-* the length of the memory is declared after the variable name, and starts with 0, the right index being the highest index of the vector, <syntaxhighlight lang="Verilog" inline>[0:endindex]</syntaxhighlight>
+* the length of the memory is declared after the variable name, and starts with 0, the right index being the highest index of the vector, <syntaxhighlight lang="SystemVerilog" inline>[0:endindex]</syntaxhighlight>
@@ Linia 33: / Linia 33: @@
 A more flexible description employs a single memory array, declared as a vector of '''reg''' variables, and a statement that assigns the selected (addressed) element of the memory vector to the memory output.
-<syntaxhighlight lang = "verilog">
+<syntaxhighlight lang = "SystemVerilog">
 assign dout = memory[addr];
 </syntaxhighlight>
@@ Linia 54: / Linia 54: @@
 If the initialization is intended to be done for the implemented memory, the initialization process must be placed inside the memory module, in which case the memory array name is just the variable array to be initialized:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 initial $readmemb("../../meminit.txt", mem);
 </syntaxhighlight>
@@ Linia 81: / Linia 81: @@
 * Start a new project, '''rom''', in a newly created folder '''rom'''
-* Create a new verilog file ''rom.v'' that describes a 16x8 ROM using a vector variable and a continuous assignment.
+* Create a new verilog file ''rom.sv'' that describes a 16x8 ROM using a vector variable and a continuous assignment.
 * Create a testbench, '''rom_tb''', that drives the input of '''rom''' with a sequence of addresses from 0 to highest one. Run simulation.
 * Open a text editor, write some values in binary format on successive lines, and save the file into the ''rom'' folder with the name ''meminit.txt''
 * In the testbench module add an '''initial''' process with a single statement that calls the system task for memory initialization. Run simulation.
-* Assign the segments of Digit0 from DE1-SOC display to '''dout''', and SW[3] ... SW[0] switches to '''addr'''.
+* Assign the segments of a display to '''dout''', and 4 switches, from SW3 to SW0, to '''addr'''.
 * In the '''rom''' module add an '''initial''' process with a single statement that calls the system task for memory initialization. Pay atention how its second argument is given - the array variable is now directly accesible. Compile the project and program the FPGA.
@@ Linia 97: / Linia 97: @@
 The FPGA has dedicated blocks for memory implementation, the so called ''ram blocks'', or ''ramblocks''. In order for the synthesis to map a memory description to a ''ramblock'', the sequential description must conform to a template:
-<syntaxhighlight lang="Verilog">
+<syntaxhighlight lang="SystemVerilog">
 always @(posedge clk) begin
      if(~we)                   // if write is enabled,
@@ Linia 106: / Linia 106: @@
 * Start a new project, '''ram''', in a new folder '''ram'''
-* Create a new verilog file ''ram.v'' that describes a 16x4 RAM using a vector variable and a sequential '''always''' process that assigns to '''rdata''' output the value of the memory location selected by '''addr'''. In the same process update the same location with '''wdata''' value if '''we''' input is active (active at '''0''').
+* Create a new verilog file ''ram.sv'' that describes a 16x4 RAM using a vector variable and a sequential '''always''' process that assigns to '''rdata''' output the value of the memory location selected by '''addr'''. In the same process update the same location with '''wdata''' value if '''we''' input is active (active at '''1''').
 * Create a testbench, '''ram_tb''', which writes some data to four addresses, and then reads the same addresses in the same order, as indicated in the waveforms below. Don't forget the clock! Run simulation and check that the written data are correctly read afterwards.
-* Assign LEDs to the output, switches to the '''addr''' and '''wdata''' inputs, a push button (KEY0) to the write enable input (the push button generates '''0''' if pressed), and a 50 MHz source clock to '''clk''' input.
+* Assign LEDs to the output, switches to the '''addr''' and '''wdata''' inputs, a push button to the write enable input, and the board's source clock to '''clk''' input.
 * Compile, program the FPGA and test the RAM. Set switches to an address and a data value, then briefly push the write enable button. The LEDs will change accordingly. Change the address and data and push again the write enable button. Change back the address switches and see if the previously written configuration reappears on LED.

@@ Linia 1: / Linia 1: @@
-A random access memory is an address based data storage block, with a highly regular structure, which may be logically defined either as a bidimensional array of bits, or a unidimensional list of data words. Each row of the array, or each item of the list has a unique address. The addresses form a contiguous set of integers, starting from zero and running up to the highest address which defines the size of the address space, usually a power of 2. The memory capacity is therefore the number of address locations, N, times the width of the memory location (or of the memory word), W. These two numbers are the main parameters of any memory:
+A random access memory is an address-based data storage block, with a highly regular structure, which may be logically defined either as a bi-dimensional array of bits, or a uni-dimensional list of data words. Each row of the array, or each item of the list has a unique address. The addresses form a contiguous set of integers, starting from zero and running up to the highest address which defines the size of the address space, usually a power of 2. The memory capacity is therefore the number of address locations, N, times the width of the memory location (or of the memory word), W. These two numbers are the main parameters of any memory:
 * N - the number of address locations, also the number of words;
 * W - the number of bits for each location, or the data word width;
@@ Linia 113: / Linia 113: @@
 [[Fișier: appl8_ram_wave.png]]
+<!--
 == Exercise 3 ==
 === Programmable display ===
@@ Linia 131: / Linia 131: @@
 * Assign swithces, push button, clock source and digit display as shown.
 * Compile, program the FPGA, and play with the board switches and buttons.