Applications 9 - Revizia istoricului

Zhascsi: /* State transitions */

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State transitions

Zhascsi: /* Outputs */

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Outputs

Zhascsi: /* Outputs */

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Outputs

Zhascsi: /* State coding */

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State coding

Zhascsi: /* Outputs */

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Outputs

Zhascsi: /* State transitions */

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State transitions

Zhascsi: /* Exercise 2 */

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Exercise 2

Zhascsi: /* Exercise 1 */

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Exercise 1

Zhascsi: /* State transitions */

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State transitions

Zhascsi: /* Outputs */

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Outputs

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 * All assignments inside the sequential process are done with the nonblocking assignment operator, <syntaxhighlight lang="Verilog" inline><=</syntaxhighlight>
 * Don't forget the '''default''' case!
-* The '''reg''' variable for the state must be declared with the required number of bits, which is the same as the number of bits declared for each value of the state value parameters.
+* The state variable must be declared with the required number of bits, which is the same as the number of bits declared for each value of the state value parameters.
 === Outputs ===

← Versiunea anterioară		Versiunea de la data 29 aprilie 2025 23:32
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	Since the delayed Mealy outputs depend both on the previous state AND the previous input values (at the last transition) they are described inside a sequential '''always_ff''' process.		Since the delayed Mealy outputs depend both on the previous state AND the previous input values (at the last transition) they are described inside a sequential '''always_ff''' process.
−	~~The outputs must be declared of '''reg''' type.~~

	<syntaxhighlight lang = "SystemVerilog">		<syntaxhighlight lang = "SystemVerilog">

@@ Linia 90: / Linia 90: @@
 </syntaxhighlight>
-The combinational '''always''' process is preferred when state values are easier to group by states:
+The combinational '''always_comb''' process is preferred when state values are easier to group by states:
 <syntaxhighlight lang = "SystemVerilog">
 always_comb begin

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 * Local parameter declarations are the first statements after the module interface. The order of statements for a module should be the following:
 # '''module'''
-# interface declaration (the list of inputs and outputs)
+# interface declaration (inputs and outputs)
 # localparam declarations
-# internal wire and reg declarations
+# internal signal declarations
-# description (structural with instantiations or behavioral with always processes and continuos assignments)
+# description (structural with instantiations, or behavioral with always processes and continuous assignments)
 # '''endmodule'''

@@ Linia 82: / Linia 82: @@
 === Outputs ===
-Since Moore outputs depend only on state they are described either through continuous assignments, or inside a combinational '''always''' process.
+Since Moore outputs depend only on state they are described either through continuous assignments, or inside a combinational '''always_comb''' process.
 If continuous assignments are used, the outputs are assigned logic expressions based on state:

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 === State transitions ===
-All transitions are grouped in a single sequential '''always''' process, with a '''case''' statement that groups transitions by current state.
+All transitions are grouped in a single sequential '''always_ff''' process, with a '''case''' statement that groups transitions by current state.
 The combinational function that computes the next state (the transition function) is implicitly described by the case statement and the statements for each case.
-The state is updated sequentially because the '''always''' process is sensitive only to clock edges.
+The state is updated sequentially because the '''always_ff''' process is sensitive only to the active clock edges.
 <syntaxhighlight lang = "SystemVerilog">

@@ Linia 118: / Linia 118: @@
 == Exercise 2 ==
-''Design an automaton that determines the order in which two buttons are pressed. The buttons generate logic signals, '''a''' and '''b''', that are '''1''' if the corresponding button is pressed. The automaton has two logic outputs, '''Y1''' and '''Y2'''. '''Y1''' is asserted if '''a''' was pressed first, followed by '''b'''. '''Y2''' is asserted if '''b''' was pressed first, followed by '''a'''. The outputs are asserted for ONLY ONE CLOCK CYCLE. The reset is active '''0'''.''
+''Design an automaton that determines the order in which two buttons are pressed. The buttons generate logic signals, '''a''' and '''b''', that are '''1''' if the corresponding button is pressed. The automaton has two logic outputs, '''Y1''' and '''Y2'''. '''Y1''' is asserted if '''a''' was pressed first, followed by '''b'''. '''Y2''' is asserted if '''b''' was pressed first, followed by '''a'''. The outputs are asserted for ONLY ONE CLOCK CYCLE.
 [[Fișier: appl9_ex1.png]]
@@ Linia 136: / Linia 136: @@
 === Outputs ===
-Since the delayed Mealy outputs depend both on the previous state AND the previous input values (at the last transition) they are described inside a sequential '''always''' process.
+Since the delayed Mealy outputs depend both on the previous state AND the previous input values (at the last transition) they are described inside a sequential '''always_ff''' process.
 The outputs must be declared of '''reg''' type.
@@ Linia 173: / Linia 173: @@
 [[Fișier: appl9_mealy_wave.png]]
 == Exercise 3 ==

@@ Linia 8: / Linia 8: @@
 == Exercise 1 ==
-''Design an automaton that determines the order in which two buttons are pressed. The buttons generate logic signals, '''a''' and '''b''', that are '''1''' if the corresponding button is pressed. The automaton has two logic outputs, '''Y1''' and '''Y2'''. '''Y1''' is asserted if '''a''' was pressed first, followed by '''b'''. '''Y2''' is asserted if '''b''' was pressed first, followed by '''a'''. The outputs remain asserted until reset. The reset is active '''0'''.''
+''Design an automaton that determines the order in which two buttons are pressed. The buttons generate logic signals, '''a''' and '''b''', that are '''1''' if the corresponding button is pressed. The automaton has two logic outputs, '''Y1''' and '''Y2'''. '''Y1''' is asserted if '''a''' was pressed first, followed by '''b'''. '''Y2''' is asserted if '''b''' was pressed first, followed by '''a'''. The outputs remain asserted until reset.
 [[Fișier: appl9_ex1.png]]
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 * Design a testbench with the input signals generated as in the figure below.
 * Run simulation. If the design is correct the outputs should appear as in the figure.
 * To implement the design assign BTN0, BTN1 and BTN2 to '''rst''', '''a''', and '''b''' inputs. Assign LED1 and LED2  to '''y1''' and '''y2''' outputs.

@@ Linia 47: / Linia 47: @@
 The state is updated sequentially because the '''always''' process is sensitive only to clock edges.
-<syntaxhighlight lang = "verilog">
+<syntaxhighlight lang = "SystemVerilog">
-always @(posedge clk) begin
+always_ff @(posedge clk) begin
      if(~rst)
          state <= STATE_S;
@@ Linia 79: / Linia 79: @@
 * Don't forget the '''default''' case!
 * The '''reg''' variable for the state must be declared with the required number of bits, which is the same as the number of bits declared for each value of the state value parameters.
 === Outputs ===