Automata - Revizia istoricului

Cbira: Cbira a redenumit pagina Automata. în Automata

2018-05-11T18:10:35Z

Cbira a redenumit pagina Automata. în Automata

Cbira: /* Example */

2018-05-11T18:07:23Z

Example

Cbira: /* Example */

2018-05-10T07:08:37Z

Example

Cbira la 10 mai 2018 07:03

2018-05-10T07:03:29Z

Cbira: /* The interface of an automaton */

2018-05-10T07:03:17Z

The interface of an automaton

Cbira: /* The interface of an automaton */

2018-05-10T07:02:34Z

The interface of an automaton

Cbira: Pagină nouă: Generic block diagram for Moore and Mealy The automaton is a sequential circuit, used to program a sequence of operations. An automaton is defined by t...

2018-05-10T07:02:14Z

Pagină nouă: thumb | Generic block diagram for Moore and Mealy The automaton is a sequential circuit, used to program a sequence of operations. An automaton is defined by t...

Pagină nouă

[[File: fsm.png | thumb | Generic block diagram for Moore and Mealy]]

The automaton is a sequential circuit, used to program a sequence of operations. An automaton is defined by the following elements:
* a set of input values (which for the circuits are input ports);
* a set of output values (which for the circuits are output ports);
* a lot of states that alternate over time and only one of which is active at a given time (which is stored in an internal register for the circuits);
* a state transition function, which calculates the next state of the automaton according to the current status and the input values (which for the circuits is a combination module);
* an output transition function that calculates the next output value, depending on the current state (for Moore type machines), or the current state and input values (for Mealy machines) (which for circuits is a combination module).

At each clock queue, the machine translates to the next state, calculated by the combined logic circuit.

'''Note:''' The total number of states available to an automaton is given by the number of the status register bits.

'''Remark:''' There are state coding modes that allow for safe transition in the case of asynchronous inputs. Fortunately, modern synthesis programs automatically detect these cases and recodify the corresponding states.

== The interface of an automaton ==

The interface of an automaton is composed of the following ports:
* clock signal as input;
* Reset signal as input;
* a number of inputs with different functions;
* a number of outputs with different functions;

</p> <p class = "rule"> <font color = "red"> '''Rule:''' </font> When the reset is active, the machine switches to one of the states, which is the initial state. </ Div>

== Implementing a machine ==

The implementation part of an automaton is composed of the definition of a '''state register''' on a sufficient number of bits to be able to encode the number of states desired, and the definition of states and output transitions implemented by a block '' ' always' '' sequentially and a sub-block '''case'''.

'''Note:''' If the machine reaches an undefined state, then the following transition is in a defective state as a state of error, or in the initial state, as the case may be. The undefined states are those in the block '''case''' that are treated by the '''default''' condition.

== Example ==

For example, the machine described in the diagram of the following figure, where the output is even the state code:

[[File: fsm1.png | Automated example chart]]

The code describing the machine is the following:

<syntaxhighlight lang = "Verilog">
`define STAREA_0 3'b000
define STAREA_1 3'b001
`define STAREA_2 3'b010
define STAREA_3 3'b011
`define STAREA_4 3'b100

module TestFSM (
output [2: 0] out,
input [3: 0] in0,
input in1,
input clock,
input reset
)

reg [2: 0] state;

always @ (posedge clock) begin
if (reset) begin
state <= `STAREA_0;
end else begin
houses (state)
`STAREA_0: begin
if (in0 == 4'd12) begin
states <= `STAREA_1;
end else begin
state <= `STAREA_4;
end
end
`STAREA_1: begin
if (in1) begin
state <= `STAREA_0;
end else begin
state <= `STAREA_2;
end
end
`STAREA_2: begin
if (in1) begin
state <= `STAREA_0;
end else if (in0 == 4'd10) begin
state <= `STAREA_4;
end else begin
state <= `STAREA_3;
end
end
`STAREA_3: begin
if (! in1) begin
state <= `STAREA_4;
end
end
`STAREA_4: begin
state <= `STAREA_4;
end
default: begin
state <= `STAREA_0;
end
endcase
end
end

assign out = state;

endmodule
</syntaxhighlight>

← Versiunea anterioară	Versiunea de la data 11 mai 2018 18:10
(Nicio diferență)

@@ Linia 57: / Linia 57: @@
 always @ (posedge clock) begin
      if (reset) begin
-         state <= `STAREA_0;
+         state <= `STATE_0;
      end else begin

@@ Linia 39: / Linia 39: @@
 <syntaxhighlight lang = "Verilog">
-`define STAREA_0 3'b000
+`define STATE_0 3'b000
-define STAREA_1 3'b001
+'define STATE_1 3'b001
-`define STAREA_2 3'b010
+`define STATE_2 3'b010
-define STAREA_3 3'b011
+'define STATE_3 3'b011
-`define STAREA_4 3'b100
+`define STATE_4 3'b100
 module TestFSM (
-output [2: 0] out,
+        output [2:0] out,
-input [3: 0] in0,
+        input  [3:0] in0,
-input in1,
+        input in1,
-input clock,
+        input clock,
-input reset
+        input reset
+);
 reg [2: 0] state;
 always @ (posedge clock) begin
-if (reset) begin
+    if (reset) begin
-state <= `STAREA_0;
+        state <= `STAREA_0;
-end else begin
+    end else begin
-houses (state)
-`STAREA_0: begin
+    case (state)
-if (in0 == 4'd12) begin
+        `STATE_0: begin
-states <= `STAREA_1;
+             if (in0 == 4'd12) begin
-end else begin
+                  state <= `STATE_1;
-state <= `STAREA_4;
+             end else begin
-end
+                  state <= `STATE_4;
-end
+             end
-`STAREA_1: begin
+         end
 if (in1) begin
-state <= `STAREA_0;
+        `STATE_1: begin
-end else begin
+             if (in1) begin
-state <= `STAREA_2;
+                  state <= `STATE_0;
-end
+             end else begin
-end
+                  state <= `STATE_2;
-`STAREA_2: begin
+             end
-if (in1) begin
+         end
-state <= `STAREA_0;
-end else if (in0 == 4'd10) begin
+         `STATE_2: begin
-state <= `STAREA_4;
+             if (in1) begin
-end else begin
+                  state <= `STATE_0;
-state <= `STAREA_3;
+             end else if (in0 == 4'd10) begin
-end
+                  state <= `STATE_4;
-end
+             end else begin
-`STAREA_3: begin
+                 state <= `STATE_3;
-if (! in1) begin
+             end
-state <= `STAREA_4;
+         end
 end
-end
+         `STATE_3: begin
-`STAREA_4: begin
+             if (! in1) begin
-state <= `STAREA_4;
+                 state <= `STATE_4;
-end
+             end
-default: begin
+         end
-state <= `STAREA_0;
-end
+         `STATE_4: begin
-endcase
+             state <= `STATE_4;
 end
 end

@@ Linia 10: / Linia 10: @@
 At each clock queue, the machine translates to the next state, calculated by the combined logic circuit.
-'''Note:''' The total number of states available to an automaton is given by the number of the status register bits.
+'''Remark:''' The total number of states available to an automaton is given by the number of the status register bits.
 '''Remark:''' There are state coding modes that allow for safe transition in the case of asynchronous inputs. Fortunately, modern synthesis programs automatically detect these cases and recodify the corresponding states.

@@ Linia 17: / Linia 17: @@
 The interface of an automaton is composed of the following ports:
-* clock signal as input;
+* the clock signal as input;
-* Reset signal as input;
+* the reset signal as input;
 * a number of inputs with different functions;
 * a number of outputs with different functions;
-</p> <p class = "rule"> <font color = "red"> '''Rule:''' </font> When the reset is active, the machine switches to one of the states, which is the initial state. </div>
+<p class = "rule"> <font color = "red"> '''Rule:''' </font> When the reset is active, the machine switches to one of the states, which is the initial state. </div>
 == Implementing a machine ==