DIC Lab Work 1 - Revizia istoricului

Zhascsi: /* Exercise 6 */

2019-02-24T15:29:43Z

Exercise 6

Zhascsi: /* Exercise 6 */

2019-02-24T15:29:32Z

Exercise 6

Zhascsi: /* Exercise 5 */

2019-02-24T15:29:05Z

Exercise 5

Cbira la 30 mai 2018 09:19

2018-05-30T09:19:10Z

Cbira: /* Example */

2018-05-30T09:15:44Z

Example

Cbira: /* Exercise 1 */

2018-05-30T09:15:10Z

Exercise 1

Cbira: /* Example */

2018-05-30T09:14:08Z

Example

Cbira: /* Notions and Knowledge Required */

2018-04-26T07:10:02Z

Notions and Knowledge Required

Cbira la 26 aprilie 2018 07:06

2018-04-26T07:06:44Z

Cbira: /* Recommendations for Teachers */

2018-04-11T22:19:45Z

Recommendations for Teachers

@@ Linia 71: / Linia 71: @@
 Implement the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''y''', with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW5, SW4, and SW1, and output y to LEDR7.
-[[File: lab1_ex6.png|center|300px]]
+[[File: lab1_ex6.png|center|400px]]
 == Submission of Exercise Solving ==

@@ Linia 71: / Linia 71: @@
 Implement the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''y''', with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW5, SW4, and SW1, and output y to LEDR7.
-[[File: lab1_ex6.png]]
+[[File: lab1_ex6.png|center|300px]]
 == Submission of Exercise Solving ==

@@ Linia 65: / Linia 65: @@
 Implement the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''y''', with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW5, SW6, and SW7 respectively, and output y to LEDR4.
-[[File: lab1_ex5.png]]
+[[File: lab1_ex5.png|center|300px]]
 == Exercise 6 ==

@@ Linia 32: / Linia 32: @@
 Implement the project on the DE1 board and observe the circuit functionality described by the Quartus II project.
-The list of pins to which I /O devices are connected to the DE1 board are described [http://wiki.dcae.pub.ro/images/f/fc/Pinii_la_care_sunt_conectati_Dispozitivele_I-O_pe_placa_experimentala_DE1.pdf here]
+The list of pins to which I /O devices are connected to the DE1 board are described
 == Exercise 1 ==
@@ Linia 42: / Linia 45: @@
 == Exercise 2 ==
-Make the verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''q''' with the functionality in the diagram below. Implement the circuit on the DE1 board by connecting inputs a, b, c to SW3, SW4, and SW7, and output q to LEDR7.
+Implement the verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''q''' with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW3, SW4, and SW7, and output q to LEDR7.
 [[File: lab1_ex2.gif]]
@@ Linia 48: / Linia 51: @@
 == Exercise 3 ==
-Make the verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''q''' with the functionality in the diagram below. Implement the circuit on the DE1 board by connecting inputs a, b, c to SW1, SW6, and SW7, and output q to LEDG3.
+Implement the verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''q''' with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW1, SW6, and SW7, and output q to LEDR3.
 [[File: lab1_ex3.jpg]]
@@ Linia 54: / Linia 57: @@
 == Exercise 4 ==
-Make the description in Verilog of the module with the inputs '''a''', '''b''', '''c''' and the output '''z''' with the functionality in the diagram below. Implement the circuit on the DE1 board by connecting inputs a, b, c to SW3, SW4, and SW5, and output z to LEDR6.
+Implement the description in Verilog of the module with the inputs '''a''', '''b''', '''c''' and the output '''z''' with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW3, SW4, and SW5, and output z to LEDR6.
 [[File: lab1_ex4.png]]
@@ Linia 60: / Linia 63: @@
 == Exercise 5 ==
-Make the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''y''', with the functionality in the diagram below. Implement the circuit on the DE1 board by connecting inputs a, b, c to SW5, SW6, and SW7 respectively, and output y to LEDG4.
+Implement the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''y''', with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW5, SW6, and SW7 respectively, and output y to LEDR4.
 [[File: lab1_ex5.png]]
@@ Linia 66: / Linia 69: @@
 == Exercise 6 ==
-Make the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''y''', with the functionality in the diagram below. Implement the circuit on the DE1 board by connecting inputs a, b, c to SW5, SW4, and SW1, and output y to LEDR7.
+Implement the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''y''', with the functionality in the diagram below. Implement the circuit on the DE1/De1-SoC board by connecting inputs a, b, c to SW5, SW4, and SW1, and output y to LEDR7.
 [[File: lab1_ex6.png]]

@@ Linia 14: / Linia 14: @@
 <syntaxhighlight lang="Verilog">
-OrGate modules (
+module OrGate(
 output out,
 input in1,

@@ Linia 36: / Linia 36: @@
 == Exercise 1 ==
-Make the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''d''' with the functionality shown in the diagram below. Implement the circuit on the DE1 board by connecting inputs a, b, c to SW2, SW4, and SW6 respectively, and output d to LEDG2.
+Implement the Verilog description of the module with the inputs '''a''', '''b''', '''c''' and the output '''d''' with the functionality shown in the diagram below. Implement the circuit on the DE1/DE1-SoC board by connecting inputs a, b, c to SW2, SW4, and SW6 respectively, and output d to LEDR2.
 [[File: lab1_ex1.jpg]]

@@ Linia 18: / Linia 18: @@
 input in1,
 input in2
+);
 assign out=in1 | in 2;

@@ Linia 4: / Linia 4: @@
 * [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for plate DE1]
 * [http://wiki.dcae.pub.ro/images/d/d9/Lista_pinilor_pl%C4%83cii_DE1-SoC.pdf Plate pin list DE1_SOC]
-* [[Introduction. Verilog HDL and ModelSim #Introduction to Digital Circuits | Boolean Logic and Numerical Systems]]
+* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]]
 * Syntax notions [[Verilog]]

@@ Linia 1: / Linia 1: @@
 == Notions and Knowledge Required ==
-* [[Tutorial_Quartus_II | Using the Altera Quartus II Synthesis Program]]
+* [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]]
 * [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for plate DE1]
 * [http://wiki.dcae.pub.ro/images/d/d9/Lista_pinilor_pl%C4%83cii_DE1-SoC.pdf Plate pin list DE1_SOC]

← Versiunea anterioară		Versiunea de la data 11 aprilie 2018 22:19
Linia 85:		Linia 85:
	== Recommendations for Teachers ==		== Recommendations for Teachers ==

−	* Implementing a Quartus project example, going through the [[~~Tutorial_Quartus_II~~ \| tutorial]].	+	* Implementing a Quartus project example, going through the [[Quartus_II_tutorial \| tutorial]].