DIC Lab Work 3 - Revizia istoricului

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2018-04-26T07:10:58Z

Notions and Knowledge Required

Cbira la 26 aprilie 2018 07:05

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2018-04-11T23:55:08Z

Notions and Knowledge Required

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Notions and Knowledge Required

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Cbira: /* Exercises */

2018-04-11T22:57:40Z

Exercises

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2018-04-11T22:57:12Z

Exercises

Cbira: Pagină nouă: == Notions and Knowledge Required == * Boolean logic and numbering systems * Syntax Verilog * Tutorial_Quartus_II | Using the Al...

2018-04-11T22:55:55Z

Pagină nouă: == Notions and Knowledge Required == * Boolean logic and numbering systems * Syntax Verilog * Tutorial_Quartus_II | Using the Al...

Pagină nouă

== Notions and Knowledge Required ==

* [[Introduction. Verilog HDL and ModelSim | Boolean logic and numbering systems]]
* Syntax [[Verilog]]
* [[Tutorial_Quartus_II | Using the Altera Quartus II Synthesis Program]]
* [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for plate DE1]
* [[Sequential Circuits]], [[Counter]]

== Example ==

Describe in Verilog a 32-bit counter with synchronous reset. Link the reset signal to the KEY3 button. Link the less significant 4 bits of the counter's output to the LEDG3 LEDG0 and the LEDs [26:23] on the LEDR3-LEDR0 red LEDs. Observe the variation in speed.

== Exercises ==

Describe in Verilog a circuit that generates a periodic periodic periodic signal using one of the clock signals on the DE1 plate as required by exercises 1-6. This circuit contains a reset counter '''''''''' and has a number of bits large enough to obtain the desired frequency. Write the Verilog module by following the following requirements:
* The module name must be 'counter_ks''', where k is the period indicated for each exercise
* The module interface must be composed of the following signals:
* #clock signal, called '''clk'''
* #reset signal, called '''reset'''
* #one bit output signal called '' out '''to oscillate with the required period.
The constraints for the reset signal, the LED on which the output and the clock signal are used are specified for each exercise.

For the maximum mark (10), the desired frequency signal will be generated. It will be at most 8 to generate a signal of a frequency as close as possible to this frequency using one of the counter's outputs.

=== Exercise 1 ===
Output signal has 1s.
The clock signal of the CLOCK27 will be used.
The reset input is the KEY2 button.
The output is connected to LEDR9.

=== Exercise 2 ===
The output signal has a period of 2 seconds.
The clock signal of the CLOCK24 will be used.
The reset input is the KEY0 button
The output is connected to LEDR5.

=== Exercise 3 ===
The output signal has a period of 3 seconds.
The clock signal of the CLOCK50 will be used.
The reset input is the KEY1 button.
The output is connected to LEDR0.

=== Exercise 4 ===
The output signal has a period of 2 seconds.
The clock signal of the CLOCK27 will be used.
The reset input is the KEY3 button.
The output is connected to LEDG7.

=== Exercise 5 ===
The output signal has a period of 3 seconds.
The clock signal of the CLOCK24 will be used.
The reset input is the KEY2 button.
The output is connected to LEDG0.

=== Exercise 6 ===
Output signal has 1s.
The clock signal of the CLOCK50 will be used.
The reset input is the KEY0 button.
The output is connected to LEDR4.

== Bonus Exercise ==

Implement the circuit from the previous exercise with a top module that describes structurally the principle of the frequency divider (use a counter and a circuit that resets the counter when the output reaches a certain value). In the top module, the counter and the circuit that generates the reset signal for the counter are instantiated.

== Submission of Exercises ==

For scoring, the following files will be submitted to the e-mail address indicated by the teacher.

An archive <span style="color: red; font-weight: bold"> zip </span>
* The Verilog file with the .v extension that contains the Verilog description of the circuit. If you have solved the bonus exercise you will send the 3 files.
* A constraint file with the .qsf extension
* A Quartus project file with the .qpf extension
Note that the archive will contain only the 3 files (no directories).

The subject of the email message must be in the <span style="color: red; font-weight: bold"> [Name] _ [First Name] _ [Group] _Numarator_ [ Exercise] </span> for example Petrica_Lucian_423B_7seg_4

== Recommendations for the Teaching Framework ==

Synchronous circuit concepts (front-end blocks always, non-blocking attributes) will be checked.
The idea of the frequency divider will be explained from a clock frequency different from those on the board and the students' questions will be answered.

@@ Linia 1: / Linia 1: @@
 == Notions and Knowledge Required ==
-* [[Introduction. Verilog HDL and ModelSim | Boolean logic and numbering systems]]
+* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]]
 * Verilog Syntax [[Verilog_EN]]
 * [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]]

@@ Linia 2: / Linia 2: @@
 * [[Introduction. Verilog HDL and ModelSim | Boolean logic and numbering systems]]
-* Syntax [[Verilog_EN]]
+* Verilog Syntax [[Verilog_EN]]
 * [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]]
-* [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for plate DE1]
+* [http://wiki.dcae.pub.ro/images/f/fc/Pinii_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for DE1 board], [http://wiki.dcae.pub.ro/images/3/37/Pin_Assignments_Cyclone_V_.pdf List of pins for DE1-SoC board]
 * [[Sequential Circuits]], [[The Counter]]

@@ Linia 16: / Linia 16: @@
 * The module name must be '''counter_ks''', where k is the period indicated for each exercise
 * The module interface must be composed of the following signals:
-* #clock signal, called '''clk'''
+*#clock signal, called '''clk'''
-* #reset signal, called '''reset'''
+*#reset signal, called '''reset'''
-* #one bit output signal called ''' out '''to oscillate with the required period.
+*#one bit output signal called ''' out '''to oscillate with the required period.
 The constraints for the reset signal, the LED on which the output and the clock signal are used are specified for each exercise.

@@ Linia 3: / Linia 3: @@
 * [[Introduction. Verilog HDL and ModelSim | Boolean logic and numbering systems]]
 * Syntax [[Verilog]]
-* [[Tutorial_Quartus_II | Using the Altera Quartus II Synthesis Program]]
+* [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]]
 * [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for plate DE1]
 * [[Sequential Circuits]], [[Counter]]