DIC Lab Work 5 - Revizia istoricului

Cbira: /* Exercise */

2018-05-30T09:36:04Z

Exercise

2018-05-30T09:35:33Z

Exercise

2018-05-30T09:34:32Z

Example

2018-05-30T08:56:08Z

Exercise

2018-05-30T08:55:36Z

Exercise

2018-05-11T19:37:42Z

Exercise

2018-05-11T19:37:17Z

Notions and Knowledge Required

2018-04-26T07:11:33Z

Notions and Knowledge Required

2018-04-26T07:05:51Z

Notions and Knowledge Required

2018-04-26T07:02:26Z

Notions and Knowledge Required

@@ Linia 76: / Linia 76: @@
 ** ADR at SW3-0,
 ** WEN la KEY3,
-** DOED to LEDR3-0,
+** DOUT to LEDR3-0,
 ** clock input at CLOCK_50.
-* Schedule the FPGA board; Write the RAM with the values required to produce DOUT a sequence of numbers indicated by the teacher.
+* Program the FPGA board; Write the RAM with the values required to produce DOUT a sequence of numbers indicated by the teacher.
 == Submission of Exercises ==

@@ Linia 41: / Linia 41: @@
 endmodule
 module ROM(
      input [3: 0] in,

@@ Linia 12: / Linia 12: @@
 * It will describe in Verilog a 16x4b RAM with a read-write port. Reading is synchronous.
-* The necessary debugging to connect will be written
+* The necessary pin connections will be written
-** Address to SW7-4 and date of entry to SW3-0.
+** the address to SW7-4 and date of entry to SW3-0.
-** writing activation signal at one of the buttons (KEY0 ... KEY3).
+** the write enable signal at one of the buttons (KEY0 ... KEY3).
-** Output memory at LEDR3-0.
+** the output at LEDR3-0.
 ** memory clock input to one of the DE1 plate oscillators.
-* Schedule the FPGA board, and using the switches and buttons on the board, write 3, 6, and 10 with the values 2, 1 and 7, then read them in the same order. Notice, using the LEDs of the board, if the memory has been stored.
+* Program the FPGA, and using the switches and buttons on the board, write 3, 6, and 10 with the values 2, 1 and 7, then read them in the same order. Notice, using the LEDs of the board, if the memory has been written.
 == Exercise ==

@@ Linia 36: / Linia 36: @@
      input clk,
      output reg [31: 0] cnt
+);
 always @ (posedge clk) cnt <= cnt + 1;
@@ Linia 45: / Linia 45: @@
      input [3: 0] in,
      output reg [3: 0] out
+);
 always @ (in)

@@ Linia 42: / Linia 42: @@
 endmodule
-ROM modules (
+module ROM(
      input [3: 0] in,
      output reg [3: 0] out
@@ Linia 48: / Linia 48: @@
 always @ (in)
-     houses (in)
+     case (in)
 : out=4'b1010;
 : out=4'b0110;

@@ Linia 68: / Linia 68: @@
 endmodule
-<syntaxhighlight>
+</syntaxhighlight>
 * Write the constraints required to connect the TOP module ports:

← Versiunea anterioară		Versiunea de la data 11 mai 2018 19:37
Linia 1:		Linia 1:
−	== Notions and Knowledge ~~Required~~ ==	+	== Required Notions and Knowledge ==

	* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases\|Boolean logic and numbering systems]]		* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases\|Boolean logic and numbering systems]]

@@ Linia 1: / Linia 1: @@
 == Notions and Knowledge Required ==
-* [[Introduction. Verilog HDL and ModelSim | Boolean logic and numbering systems]]
+* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]]
 * Verilog Syntax [[Verilog_EN]]
 * [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]]

@@ Linia 3: / Linia 3: @@
 * [[Introduction. Verilog HDL and ModelSim | Boolean logic and numbering systems]]
 * Verilog Syntax [[Verilog_EN]]
-* [[Tutorial_Quartus_II | Using the Altera Quartus II Synthesis Program]]
+* [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]]
 * [http://wiki.dcae.pub.ro/images/f/fc/Pinii_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for DE1 board], [http://wiki.dcae.pub.ro/images/3/37/Pin_Assignments_Cyclone_V_.pdf List of pins for DE1-SoC board]
 * [[Sequential Circuits]]