DIC Seminar 1 - Revizia istoricului

Cbira la 27 aprilie 2018 20:11

2018-04-27T20:11:15Z

Cbira: /* Notions and Knowledge Required */

2018-03-29T08:50:12Z

Notions and Knowledge Required

Cbira la 29 martie 2018 08:49

2018-03-29T08:49:45Z

Cbira: /* Exercise 3 */

2018-03-29T08:37:59Z

Exercise 3

Cbira la 29 martie 2018 08:37

2018-03-29T08:37:25Z

Cbira la 29 martie 2018 08:34

2018-03-29T08:34:50Z

Cbira la 29 martie 2018 08:34

2018-03-29T08:34:06Z

Cbira la 29 martie 2018 08:32

2018-03-29T08:32:48Z

Cbira: Pagină nouă: In this seminar you will learn to describe some simple digital circuits in Verilog language and use the Quartus II and ModelSim programs. '' 'Keywords:' '' logical gates, ports,...

2018-03-29T08:29:32Z

Pagină nouă: In this seminar you will learn to describe some simple digital circuits in Verilog language and use the Quartus II and ModelSim programs. '' 'Keywords:' '' logical gates, ports,...

Pagină nouă

In this seminar you will learn to describe some simple digital circuits in Verilog language and use the Quartus II and ModelSim programs.

'' 'Keywords:' '' logical gates, ports, waveform, project, mode, instantiation, testbench

Verilog syntax: '' '' 'module' ',' 'wire' ',' 'reg' ',' 'initial' ',' 'stop' '

Verilog is a hardware description language. In this language we can describe digital circuits as in Figure 1.

== Notions and Knowledge Required ==

* [[Introduction. Verilog HDL and ModelSim # Introduction to Digital Circuits | Boolean Logic and Numerical Systems]]
* Syntax notions [[Verilog]]

== Exercise 1 ==

Figure 1 is a schematic diagram of a digital circuit containing logical gates. Describe this schema in Verilog.

[[File: sem1ex1.png | Block schema for example 1]]

'' 'Explanations' '': The elementary logic gates are predefined in Verilog: '' 'not' '', '' 'and' '', '' 'nand' 'nor' '', '' 'xor' '', '' 'nxor' ''. The correct syntax is, for instantiating a '' 'and' '' gate:

<syntaxhighlight lang = "verilog">
and node_name (output, input_1, input_2, ...) entry_n);
</ Syntaxhighlight>

== Exercise 2 ==

Create a Verilog file describing the circuit from exercise 1.

'''Explanations:'''
The description of a circuit includes:
* interface (input and output ports declaration)
* description of the function or circuit diagram

In Verilog, circuit descriptions are made up of modules. The syntax is the following:

<syntaxhighlight lang = "verilog">
module_meu (port_port) module; / * ports are external circuit connections * /

// first report ports
// Then give the functional or structural details
endmodule
</ Syntaxhighlight>

== Exercise 3 ==

Generate the waveforms in the following figures in the simulator.

1. Signal i0:

[[File: cid_sem1_img2.png | Signal i0]]

2. Two signals, i0 and i1:

[[File: cid_sem1_img3.png | Signals i0 and i1]]

Three signals:

[[File: cid_sem1_img4.png | Three Signs]]

 Resolve Item 1: 

It will write a new source file that has no external ports (because it does not describe a circuit).

[[File: cid_sem1_img5.png | Source Code Exercise 3]]

== Example 4 ==
Simulate the operation of the module from exercise 2 by applying the signals from exercise 3 - point 3.
Knowing that this circuit is a multiplexer (circuit selection), analyze the waveforms to see if they are correct. Modify the waveform at input s and check the correct operation.

'' 'Explanation:' '' To simulate the operation of a circuit, we need to build a testbench described in a new module. We apply the respective signals to the input of the tested circuit - we instantiate that circuit. We simulate the test module and then analyze the waveforms to see if they correspond to the implemented function.

== Exercise 5 ==

Draw the schema described by the following Verilog code:

<syntaxhighlight lang = "verilog">
circuit1 ana (.in1 (a), .in2 (b), .out1 (w), .out2 (en));
circuit2 doru (.in3 (w), .in4 (b), .out (c));
circuit3 zuzu (.in0 (en), .in1 (c), .out (out));
</ Syntaxhighlight>

... where modules have ports declared as follows:

<syntaxhighlight lang = "verilog">
module circuit1 (
input in1, in2,
output out1,
output out2);
...
endmodule

module circuit2 (
input in3, in4,
output out);
...
endmodule

module circuit3 (
input in1,
input in0,
output out);
...
endmodule
</ Syntaxhighlight>

== The main concepts of Verilog introduced in this seminar ==

1. '' 'Circuit descriptions in Verilog are made up of' 'modules''. '' ''
Any module starts with the module word and ends with endmodules. Modules can not overlap and can not be included in each other.

<syntaxhighlight lang = "verilog">
module_meu (port_port) module; / * ports are external circuit connections * /

...... // first report ports
...... then give the functional or structural details
endmodule
</ Syntaxhighlight>

2. The ports of a circuit can be declared
* in the module body
* Compact in the port list.
Entries to Verilog are declared with the word '' input '', outputs are '' output ''.

 Version 1 (Verilog '95) 
<syntaxhighlight lang = "verilog">
module circuit (a, b, c, out);
input a, b, c; // we can put more on the same line, separated by,
output out;
.....
endmodule
</ Syntaxhighlight>

 Option 2 (Verilog 2001) 
<syntaxhighlight lang = "verilog">
module circuit (
input a, // write with tabs to be visible
input b,
input c,
output out);
...
endmodule
</ Syntaxhighlight>

If we have several similar entries we can also write:
<syntaxhighlight lang = "verilog">
module circuit (
input a, b, c,
output out);
...
endmodule
</ Syntaxhighlight>

3. '' 'The code lines in Verilog end with'; '' '' (there is also excellent
A

@@ Linia 11: / Linia 11: @@
 == Notions and Knowledge Required ==
-* [[Introduction. Verilog HDL and ModelSim # Introduction to Digital Circuits | Boolean Logic and Numerical Systems]]
+* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]]
 * Syntax notions [[Verilog_EN]]

@@ Linia 12: / Linia 12: @@
 * [[Introduction. Verilog HDL and ModelSim # Introduction to Digital Circuits | Boolean Logic and Numerical Systems]]
-* Syntax notions [[Verilog_]]
+* Syntax notions [[Verilog_EN]]
 == Exercise 1 ==

@@ Linia 62: / Linia 62: @@
 [[File: cid_sem1_img4.png | Three Signs]]
-<u> Resolve Item 1: </ u>
+<u> Resolve Item 1: </u>
 It will write a new source file that has no external ports (because it does not describe a circuit).

@@ Linia 3: / Linia 3: @@
-'' 'Keywords:' '' logical gates, ports, waveform, project, mode, instantiation, testbench
+'''Keywords:''' logical gates, ports, waveform, project, mode, instantiation, testbench
-Verilog syntax: '' '' 'module' ',' 'wire' ',' 'reg' ',' 'initial' ',' 'stop' '
+Verilog syntax: '''''module'',''wire'',''reg'',''initial'',''stop''
 Verilog is a hardware description language. In this language we can describe digital circuits as in Figure 1.
@@ Linia 114: / Linia 114: @@
 == The main concepts of Verilog introduced in this seminar ==
-. '' 'Circuit descriptions in Verilog are made up of' 'modules''. '' ''
+. '''Circuit descriptions in Verilog are made up of' 'modules''. ''''
 Any module starts with the module word and ends with endmodules. Modules can not overlap and can not be included in each other.
@@ Linia 159: / Linia 159: @@
 </syntaxhighlight>
-. '' 'The code lines in Verilog end with'; '' '' (there are exceptions that we will explicitly mention, for example after the last line - '' endmodule '' above. ; "Causes an action).
+. '''The code lines in Verilog end with'; '' '' (there are exceptions that we will explicitly mention, for example after the last line - '' endmodule '' above. ; "Causes an action).
-. '' 'The comments' '' are entered with // or with /****/, they will appear in the editor of the program with another color and are ignored in simulation and synthesis.
+. '''The comments''' are entered with // or with /****/, they will appear in the editor of the program with another color and are ignored in simulation and synthesis.
-. '' 'Simulation of circuit operation' ''
+. '''Simulation of circuit operation'''
 To verify the correct operation of a circuit, we need to apply input signals to it and verify that the output is the way we expected it to be, ie, simulating it.
@@ Linia 204: / Linia 204: @@
 At all of these gates, the default is first and exit can be as many as possible.
-'' 'Note' '': The simple notes used for logical functions in the current script are not identical to the Verilog operator symbols.
+'''Note''': The simple notes used for logical functions in the current script are not identical to the Verilog operator symbols.
 {| class = "wikitable"

@@ Linia 213: / Linia 213: @@
 | OR || + || <Nowiki> | </ nowiki>
 | -
-| XOR || & Oplus; || ^
+| XOR || &oplus; || ^
 | -
 | NOT || '|| ~

@@ Linia 24: / Linia 24: @@
 <syntaxhighlight lang = "verilog">
 and node_name (output, input_1, input_2, ...) entry_n);
-</ Syntaxhighlight>
+</syntaxhighlight>
@@ Linia 44: / Linia 44: @@
 // Then give the functional or structural details
 endmodule
-</ Syntaxhighlight>
+</syntaxhighlight>
 == Exercise 3 ==
@@ Linia 82: / Linia 82: @@
 circuit2 doru (.in3 (w), .in4 (b), .out (c));
 circuit3 zuzu (.in0 (en), .in1 (c), .out (out));
-</ Syntaxhighlight>
+</syntaxhighlight>
 ... where modules have ports declared as follows:
@@ Linia 110: / Linia 110: @@
 ...
 endmodule
-</ Syntaxhighlight>
+</syntaxhighlight>
 == The main concepts of Verilog introduced in this seminar ==
@@ Linia 123: / Linia 123: @@
 ...... then give the functional or structural details
 endmodule
-</ Syntaxhighlight>
+</syntaxhighlight>
 . The ports of a circuit can be declared
@@ Linia 137: / Linia 137: @@
 .....
 endmodule
-</ Syntaxhighlight>
+</syntaxhighlight>
 <u> Option 2 (Verilog 2001) </u>
@@ Linia 148: / Linia 148: @@
 ...
 endmodule
-</ Syntaxhighlight>
+</syntaxhighlight>
 If we have several similar entries we can also write:
@@ Linia 157: / Linia 157: @@
 ...
 endmodule
-</ Syntaxhighlight>
+</syntaxhighlight>
 . '' 'The code lines in Verilog end with'; '' '' (there are exceptions that we will explicitly mention, for example after the last line - '' endmodule '' above. ; "Causes an action).
@@ Linia 178: / Linia 178: @@
 <syntaxhighlight lang = "verilog">
 ex1 UUT (port list);
-</ Syntaxhighlight>
+</syntaxhighlight>
 Ports can be connected according to their order or by explicitly defining the signals connected to each port:
@@ Linia 185: / Linia 185: @@
 ex1 dut1 (i0, i1, i2, out);
 ex1 dut1 (.a (i0), .b (i1), .s (i2), y (out));
-</ Syntaxhighlight>
+</syntaxhighlight>
 Although in version 2 we can write the ports in any order, we prefer to write them in the same order!
@@ Linia 199: / Linia 199: @@
 and P1 (out1, in1, in2, ..., ink); // for all logic gates predefined in verilog the first port is the output
 and P2 (out2, in1, in2); // Each instance must have a unique name
-</ Syntaxhighlight>
+</syntaxhighlight>
 The other logical gates are: 'nand', '' or '', '' nor '', '' xor '', '' xnor ''.

@@ Linia 130: / Linia 130: @@
 Entries to Verilog are declared with the word '' input '', outputs are '' output ''.
-<u> Version 1 (Verilog '95) </ u>
+<u> Version 1 (Verilog '95) </u>
 <syntaxhighlight lang = "verilog">
 module circuit (a, b, c, out);
@@ Linia 139: / Linia 139: @@
 </ Syntaxhighlight>
-<u> Option 2 (Verilog 2001) </ u>
+<u> Option 2 (Verilog 2001) </u>
 <syntaxhighlight lang = "verilog">
 module circuit (
@@ Linia 159: / Linia 159: @@
 </ Syntaxhighlight>
-. '' 'The code lines in Verilog end with'; '' '' (there is also excellent
+. '' 'The comments' '' are entered with // or with /****/, they will appear in the editor of the program with another color and are ignored in simulation and synthesis.
-−