DIC Seminar 2 - Revizia istoricului

Cbira: /* The case block */

2018-04-27T20:46:46Z

The case block

Cbira la 27 aprilie 2018 20:39

2018-04-27T20:39:01Z

Cbira: /* Blocks case */

2018-04-27T20:33:20Z

Blocks case

Cbira: /* Processes always */

2018-04-27T20:32:34Z

Processes always

Cbira: /* Instruction if */

2018-04-27T20:32:02Z

Instruction if

Cbira: /* Continuous assignment */

2018-04-27T20:29:05Z

Continuous assignment

Cbira la 27 aprilie 2018 20:27

2018-04-27T20:27:13Z

Cbira: /* Continuous assignment */

2018-04-27T20:24:33Z

Continuous assignment

Cbira: /* Exercise 5 */

2018-04-27T20:24:09Z

Exercise 5

Cbira: /* Exercise 5 */

2018-04-27T20:23:55Z

Exercise 5

@@ Linia 117: / Linia 117: @@
 === The ''' case ''' block ===
-The Verilog house instruction has the following format:
+The Verilog case instruction has the following format:
 <syntaxhighlight lang="verilog">

@@ Linia 137: / Linia 137: @@
 <syntaxhighlight lang="verilog">
-a_lt_b=0;
+a_lt_b = 0;
-if (a <b) a_lt_b=1;
+if (a<b) a_lt_b = 1;
-     else;
+     else ;
 </syntaxhighlight>
-* For houses, the default case is always written even though we have specified all the possible binary configurations (this is done if the value of the expression is not known, or otherwise it has the "value" x).
+For '''case''' we will always write the default case, even if we have specified all the possible binary configurations  (this is done if the value of the expression is not known, or otherwise it has the "value" x).

@@ Linia 115: / Linia 115: @@
 When simulating a circuit, all blocks are always running in parallel.
-=== Blocks '' case '' ===
+=== The ''' case ''' block ===
 The Verilog house instruction has the following format:
@@ Linia 131: / Linia 131: @@
 </syntaxhighlight>
-Like the if, case statement is used only in a block always; the variables that
+Like the if, case statement is used only in a block always; the variables that are assigned must be declared as reg.
 == Rules of Good Practice ==

@@ Linia 103: / Linia 103: @@
                     //one of the signals a, b or c
                     //Attention! y is type reg
-<syntaxhighlight>
+</syntaxhighlight>
 More simply, we can write
@@ Linia 109: / Linia 109: @@
 <syntaxhighlight lang="verilog">
 always @ (*)
-<syntaxhighlight>
+</syntaxhighlight>
 Where the notation (*) denotes any change.

@@ Linia 91: / Linia 91: @@
 </syntaxhighlight>
-Assignments in a construct of this type are sequential ('''not''' use '' assign '') and require us to declare those variables that change their value, such as 'reg'. Several instructions can be grouped into blocks using begin .... end. To describe a combinational circuit with an 'if' statement, we use the block '' always ''. Note that in Verilog generally, '''the' if 'statement is used only in blocks' 'always'''''.
+Assignments in a construct of this type are sequential ('''not''' use '''assign''') and require us to declare those variables that change their value, such as '''reg'''. Several instructions can be grouped into blocks using begin .... end. To describe a combinational circuit with an '''if''' statement, we use the block '''always'''. Note that in Verilog generally, '''the' if 'statement is used only in blocks '''always'''.
 === Processes '''always''' ===

← Versiunea anterioară		Versiunea de la data 27 aprilie 2018 20:27
Linia 91:		Linia 91:
	</syntaxhighlight>		</syntaxhighlight>

−	Assignments ~~from~~ a construct of this type are sequential ('''not''' use '' assign '') and ~~involve declaring~~ the variables	+	Assignments in a construct of this type are sequential ('''not''' use '' assign '') and require us to declare those variables that change their value, such as 'reg'. Several instructions can be grouped into blocks using begin .... end. To describe a combinational circuit with an 'if' statement, we use the block '' always ''. Note that in Verilog generally, '''the' if 'statement is used only in blocks' 'always'''''.
		+
		+	=== Processes '''always''' ===
		+
		+	In Verilog, the '' always '' statement describes a process that is executed when at least one signal from the list of sensitivities changes (the list of signals that appears in parentheses after the @ symbol).
		+
		+	<syntaxhighlight lang="verilog">
		+	always @ (a or b or c) //here is not put ";"
		+	y=a + b + c; //Because of the always block, the sequential assignment is
		+	//recalculates each time it changes
		+	//one of the signals a, b or c
		+	//Attention! y is type reg
		+	<syntaxhighlight>
		+
		+	More simply, we can write
		+
		+	<syntaxhighlight lang="verilog">
		+	always @ (*)
		+	<syntaxhighlight>
		+
		+	Where the notation (*) denotes any change.
		+
		+	When simulating a circuit, all blocks are always running in parallel.
		+
		+	=== Blocks '' case '' ===
		+
		+	The Verilog house instruction has the following format:
		+
		+	<syntaxhighlight lang="verilog">
		+	case (case_expression)
		+
		+	value1: instruction1; /* for different expression values different instr * /
		+
		+	...
		+
		+	default: instruction; /* default case for values not specified * /
		+
		+	endcase
		+	</syntaxhighlight>
		+
		+	Like the if, case statement is used only in a block always; the variables that
		+	are assigned must be declared as reg.
		+
		+	== Rules of Good Practice ==
		+	* When describing combinational circuits, the if statement is specified elsewhere, even if nothing happens. E.g:
		+
		+	<syntaxhighlight lang="verilog">
		+	a_lt_b=0;
		+	if (a <b) a_lt_b=1;
		+	else;
		+	</syntaxhighlight>
		+
		+	* For houses, the default case is always written even though we have specified all the possible binary configurations (this is done if the value of the expression is not known, or otherwise it has the "value" x).

@@ Linia 63: / Linia 63: @@
 == The main concepts of Verilog introduced in this seminar ==
-=== Continuous assignment ===
+== Continuous assignment ==
 The continuous assignment from Verilog, the 'assign' statement, is evaluated when the value of an argument changes.
@@ Linia 74: / Linia 74: @@
 is calculated again if b or c changes its value. The continuous assignment is intended to describe the operation of the combinational circuits, in which the output follows the input changes. All '' assign '' instructions run in parallel, as all components of a circuit work at the same time.
-=== Condition assignment ===
+== Condition assignment ==
 The conditional assignment instruction has the form

@@ Linia 49: / Linia 49: @@
 For numbers 10-15, we will control the display of the E symbol (for error).
-Assignment == ==
+== Assignment ==
 #Describe the function of a comparator using the assign statement or the if:

@@ Linia 44: / Linia 44: @@
 == Exercise 5 ==
-Describe a BCD transceiver - 7 segments using the 'case' statement.
+Describe a BCD transceiver - 7 segments using the '''case''' statement.
-'''''''''' The 7-segment binary transceiver has a 4-bit binary number (representing a decimal figure) and calculates at output 7 logical signals that command the 7 segments of a display. [[IO Device : 7-segment display]].
+The 7-segment binary transceiver has a 4-bit binary number (representing a decimal figure) and calculates at output 7 logical signals that command the 7 segments of a display. [[IO Device : 7-segment display]].
 For numbers 10-15, we will control the display of the E symbol (for error).
@@ Linia 58: / Linia 58: @@
 ##conditional assignment statement;
 ##assign statement and logical expressions.
-#Change example 5, assuming the input is a hexadecimal digit. '' Note: There will be no error (E) for the values 9-15 on the input, but the corresponding figures in the base 16, symbolized with A, b, C, d, E, F. '
+#Change example 5, assuming the input is a hexadecimal digit. ''' Note''': There will be no error (E) for the values 9-15 on the input, but the corresponding figures in the base 16, symbolized with A, b, C, d, E, F. '
 #Describe in Verilog a schematic that contains the incremental circuit (of example 4) and the binary transceiver - 7 segments (of example 5). Simulate the operation of this circuit.