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Exercise 2

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Cbira: Pagină nouă: In this seminar you will learn to describe Random Access (RAM) and Read Only (ROM) memories using data vectors in Verilog. '' 'Keywords' '': memory, vector, RAM, ROM Verilog Synt...

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Pagină nouă: In this seminar you will learn to describe Random Access (RAM) and Read Only (ROM) memories using data vectors in Verilog. '' 'Keywords' '': memory, vector, RAM, ROM Verilog Synt...

Pagină nouă

In this seminar you will learn to describe Random Access (RAM) and Read Only (ROM) memories using data vectors in Verilog.

'' 'Keywords' '': memory, vector, RAM, ROM

Verilog Syntax '' ':' 'readmemh' ',' 'readmemb' ',' 'parameter' '

The memories are physical data storage structures, characterized by two measures:
* the number of N words;
* the number of bits of each stored word, W;
The storage capacity is NxW bit.

Thus, you will often encounter 1024x8b memory terminology, which describes a memory with a capacity of 1024 words of 8 bits each.

The memories can be classified according to their ability to overwrite the values stored with new values:
* Random-Access memories (RAM) also allow overwriting of stored word contents;
* Read-Only memories (ROMs) only allow reading.

Memories can also be classified by their synchronous or asynchronous character:
* asynchronous - reading is done as soon as the order is presented;
* synchronous - all operations are synchronized by one of the clock signal fronts.
For reasons of physical implementation, writing is always synchronous.

Any RAM has the following set of interface signals that make up a '' 'port' 'of memory:
* address - input - specifies the index of the word we want accessed for writing or reading;
* write-in data - data that will be written to the specified index by the address;
* read data - output - the data that has been read from the specified index by the address;
* write-in command - specifies whether writing or reading is desired;
* clock signal.

Depending on the memory port configuration, some of these signals may be missing. For example, a write-only port will not have read data. Likewise, a Read-Only port will not have write data. A Read-Write port will have all these signals. The address is the signal that defines the memory port, and can not be missed.

'' 'Notes' '': Do not confuse between the ports of a Verilog module and the ports of a memory.

== Exercise 1 ==

Describe in Verilog an 8-bit 128-bit asynchronous 128-bit read-only RAM with a single Read-Write port. It will simulate the memory function by writing in three memory locations, then reading from the three memory locations and comparing the values read with the previously written values.

 Additional explanation 

A data vector will be used in Verilog:

<syntaxhighlight lang = "verilog">
reg [W-1: 0] memory [0: N-1];
</ Syntaxhighlight>

In this example we have declared a data vector called memory, which is composed of W-bit words, and has N elements. Vector elements are accessed in the following way:
* memory [3] represents the element 4 of the memory vector, which has W bits;
* memory [3] [0] represents the zero bit of the memory vector element 4.

== Exercise 2 ==
Implement a 128-bit 128-bit RAM with two ports: a write port and a synchronous read port. Test this memory.

 Additional explanation 

In order to change the size of a memory and reuse the Verilog code, we can declare the number of address bits, the number of locations, and the size of the word as parameters.
The syntax is, for example:
<syntaxhighlight lang = "verilog">
parameter adr_size = 7;
</syntaxhighlight>

== Exercise 3 ==

Implement a FIFO memory with 32 4-bit locations using the memory of exercise 2. Test the operation of this memory by writing and reading successively different values.

 Additional explanation 

First-in-first-out FIFO reads data only in the order in which it was written. Write and read operations are not performed at any address, so a FIFO memory does not have an address entry.

The ports of this memo are:

<syntaxhighlight lang = "verilog">
module memory_fifo (
input clock, rst, // clock and reset
input write_enable, // write command
read_enable, // read command
input [word_width-1: 0] data_in, // input data, here on 4 bits
output [word_width-1: 0] data_out, // output date, 4-bit here
output reg empty, // output signal that is active when the memory is empty
full, // output signal that is active when the memory is full
output reg [adr_size: 0] fifo_counter // no used locations, maximum 32

)
</syntaxhighlight>

== Exercise 4 ==

Initialize the contents of memory from exercise 3 with the system functions ''' $ readmemh () ''' and ''' $ readmemb () '''.

 Additional explanations 

Functions are used according to the following template:
<syntaxhighlight lang = "verilog">
$ readmem [hb] ("initialization file", vector name, adr1, adr2)
</syntaxhighlight>

Functions read data in hexadecimal or binary format from the specified file, and load them in the specified vector from the Verilog module, starting from address adr1 to address adr2.

The content of the file ''' memory.txt ''' (32 4-bit values in hexadecimal, one below the other):

<syntaxhighlight lang = "bash">
1
2
of
f
...
b
</syntaxhighlight>

== HOMEWORK ==

1. Change the code from Exercise 1 to deploy a synchronous reading memory.

2. Add a second read-only read-only memory to the memory described above (THEME 1) and simulate simultaneous reading from two different locations of the memory through the two ports and the situation in which one of ports write to a memory location while the second port reads from the same memory location.

3. Implement a 512x8b memory using four 128x8b memories, properly connected.

4. Implement a 128x16b memory using two 128x8b memories, properly connected.

== Rules of Good Practice ==

The port interface signals will be grouped together and will be easily identified as part of the port (e.g., addrA, dataA, weA, addrB, dataB, weB)

@@ Linia 51: / Linia 51: @@
 Implement a 128-bit 128-bit RAM with two ports: a write port and a synchronous read port. Test this memory.
-<u> Additional explanation </ u>
+<u> Additional explanation </u>
 In order to change the size of a memory and reuse the Verilog code, we can declare the number of address bits, the number of locations, and the size of the word as parameters.
@@ Linia 58: / Linia 58: @@
 parameter adr_size = 7;
 </syntaxhighlight>
 == Exercise 3 ==

@@ Linia 21: / Linia 21: @@
 For reasons of physical implementation, writing is always synchronous.
-Any RAM has the following set of interface signals that make up a '' 'port' 'of memory:
+Any RAM has the following set of interface signals that make up a '''port''' of memory:
 * address - input - specifies the index of the word we want accessed for writing or reading;
 * write-in data - data that will be written to the specified index by the address;
@@ Linia 30: / Linia 30: @@
 Depending on the memory port configuration, some of these signals may be missing. For example, a write-only port will not have read data. Likewise, a Read-Only port will not have write data. A Read-Write port will have all these signals. The address is the signal that defines the memory port, and can not be missed.
-'' 'Notes' '': Do not confuse between the ports of a Verilog module and the ports of a memory.
+'''Notes''': Do not confuse between the ports of a Verilog module and the ports of a memory.
 == Exercise 1 ==
@@ Linia 36: / Linia 36: @@
 Describe in Verilog an 8-bit 128-bit asynchronous 128-bit read-only RAM with a single Read-Write port. It will simulate the memory function by writing in three memory locations, then reading from the three memory locations and comparing the values read with the previously written values.
-<u> Additional explanation </ u>
+<u> Additional explanation </u>
 A data vector will be used in Verilog:
@@ Linia 42: / Linia 42: @@
 <syntaxhighlight lang = "verilog">
 reg [W-1: 0] memory [0: N-1];
-</ Syntaxhighlight>
+</syntaxhighlight>
 In this example we have declared a data vector called memory, which is composed of W-bit words, and has N elements. Vector elements are accessed in the following way:

@@ Linia 1: / Linia 1: @@
 In this seminar you will learn to describe Random Access (RAM) and Read Only (ROM) memories using data vectors in Verilog.
-'' 'Keywords' '': memory, vector, RAM, ROM
+'''Keywords''' : memory, vector, RAM, ROM
-Verilog Syntax '' ':' 'readmemh' ',' 'readmemb' ',' 'parameter' '
+Verilog Syntax '''readmemh''','''readmemb''','''parameter'''
 The memories are physical data storage structures, characterized by two measures: