DIC Seminar 6 - Revizia istoricului

Zhascsi: /* Example 1 */

2018-09-05T12:34:41Z

Example 1

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Example 1

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Example 1

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Example 1

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Example 1

2018-05-11T19:54:50Z

Homework

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Example 3

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Example 4

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Example 4

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Homework

@@ Linia 133: / Linia 133: @@
          state <= STATE_READ_0;
      end else begin
-         houses (state)
+         case (state)
              STATE_READ_0: if (in == 1) state <= STATE_READ_1;
              STATE_READ_1: if (in == 0) state <= STATE_ERROR;

@@ Linia 62: / Linia 62: @@
          state <= 2'b00;
      end else begin
-         houses (state)
+         case (state)
 'b00: if (in == 1) state <= 2'b01;
 'b01: if (in == 0) state <= 2'b10;

@@ Linia 48: / Linia 48: @@
 .
 <syntaxhighlight lang="verilog">
-FSM module (
+module FSM(
      input clock,
      input reset,

@@ Linia 112: / Linia 112: @@
 endmodule
 </syntaxhighlight>
-'''Notice' 'that once you get into one of the final states, the machine crashes. In order to get back to the initial state, a reset signal is required. Thus:
+'''Notice''' that once you get into one of the final states, the machine crashes. In order to get back to the initial state, a reset signal is required. Thus:
 <div class="rule"> '''Rule''': A finite automate necessarily has a reset port. When the reset is active, the machine switches to one of the states, which is so designated as the initial state. </div>
-'''Notice' 'that we have an unused state. Generally, as a rule of good practice, for all unused states, which are the case default in the house block, the next transition will always be to the initial state (reset).
+'''Notice''' that we have an unused state. Generally, as a rule of good practice, for all unused states, which are the case default in the house block, the next transition will always be to the initial state (reset).
-'''Notice' 'that states are defined as values. For a large number of states, the codes will become difficult to understand. Therefore, we introduce the following notations in the mode:
+'''Notice''' that states are defined as values. For a large number of states, the codes will become difficult to understand. Therefore, we introduce the following notations in the mode:
 <syntaxhighlight lang="verilog">

← Versiunea anterioară		Versiunea de la data 11 mai 2018 19:54
Linia 194:		Linia 194:
	== Homework ==		== Homework ==

−	'' Modify the machine from example 3 so that it can ~~have a reminder~~. ''	+	'' Modify the machine from example 3 so that it can return the change. ''

@@ Linia 157: / Linia 157: @@
 '' Make a finished machine for a car that sells CMOS chocolate, which costs $ 2.5. ''
-'' The machine accepts coins of 50 bani and 1 leu banknotes. Name the current status based on the currently accumulated amount, expressed in multiples of 50 bani (for example STATE_0_BANI, STATE_50_BANI, STATE_100_BANI, etc.). When the amount of 2.5 lei or more is reached, the machine will deliver a chocolate and will resume the process, lowering 2.5 lei from the current amount. The machine does not return the rest. ''
+'' The machine accepts coins of 50 bani and 1 leu banknotes. Name the current status based on the currently accumulated amount, expressed in multiples of 50 bani (for example STATE_0_BANI, STATE_50_BANI, STATE_100_BANI, etc.). When the amount of 2.5 lei or more is reached, the machine will deliver a chocolate and will resume the process, lowering 2.5 lei from the current amount. The machine does not return the change. ''
 '' What type of automatic did you implement? ''

@@ Linia 185: / Linia 185: @@
 We can restore the status codes as follows:
 * STATE_READ_0, encoded 2'b00
-* STATE_READ_1, coded 2'b01
+* STATE_READ_1, encoded 2'b01
-* STATE_ERROR, coded 2'b11
+* STATE_ERROR,  encoded 2'b11
 Analyze possible transitions due to asynchronous input. What do you notice?

@@ Linia 178: / Linia 178: @@
 In our first example, we had 3 states:
 * STATE_READ_0, encoded 2'b00
-* STATE_READ_1, coded 2'b01
+* STATE_READ_1, encoded 2'b01
-* STATE_ERROR, coded 2'b10
+* STATE_ERROR,  encoded 2'b10
 It can be noticed here that the STATE_ERROR state is adjacent to state STATE_READ_1, but their coding differs by both bits, so it is not a Gray code. If, say, we are in the STATE_READ_1 state (2'b01) and the input of the machine is 1, then the CLC that calculates the next state will output 2'b01. But when the input of the machine changes to 0, then this change propagates through gates to the output of the CLC, changing its value to 2'b10 (error state). Yet we know that these two signals can not reach exactly the same time, so perhaps the least significant bit to change the first case in which, for a very short time, CLC's output will be 2'b00 up when it reaches the correct value of 2'b10. Similarly, the most significant bit can be changed first, leading to the value in 2'b11 until it stabilizes again in 2'b10. In both these cases, if the wrong value is stored in the status register, this implies a transition erroneous times in STATE_READ_0 STATE_READ_1 state or invalid state 2'b11.

← Versiunea anterioară		Versiunea de la data 11 mai 2018 19:53
Linia 194:		Linia 194:
	== Homework ==		== Homework ==

−	'' Modify the machine from example 3 so that it can ~~rest~~. ''	+	'' Modify the machine from example 3 so that it can have a reminder. ''