Digital Integrated Circuits (seminar) - Revizia istoricului

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Cbira: Pagină nouă: Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student w...

2018-04-26T07:19:51Z

Pagină nouă: Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student w...

Pagină nouă

Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student with Verilog language, as well as digital circuits synthesis and simulation (QuartusII or ModelSim) .

* [[CID Seminar 1]] - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation)
* [[CID Seminar 2]] - Conditioned instructions, using the 'always' instruction to define combinational circuits
* [[CID Seminar 3]] [[CID_Seminar_EN]] - Sequential circuits (clock signal, '''always''' and ''' initial ''' vs. '''assign'''
* [[CID Seminar 4]] - Numerals and counting circuits
* [[CID Seminar 5]] - Description of memories in Verilog
* [[CID Seminar 6]] - Finite automata

You can dowload the programs used on the Altera website:
https://dl.altera.com/13.0sp1/?edition=web

@@ Linia 1: / Linia 1: @@
 Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student with Verilog language, as well as digital circuits synthesis and simulation (QuartusII or ModelSim) .
-* [[CID Seminar 1]] - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation)
+* [[DIC Seminar 1]] - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation)
-* [[CID Seminar 2]] - Conditioned instructions, using the 'always' instruction to define combinational circuits
+* [[DIC Seminar 2]] - Conditioned instructions, using the 'always' instruction to define combinational circuits
 * [[DIC Seminar 3]] - Sequential circuits (clock signal, '''always''' and ''' initial ''' vs. '''assign'''
-* [[CID Seminar 4]] - Numerals and counting circuits
+* [[DIC Seminar 4]] - Numerals and counting circuits
-* [[CID Seminar 5]] - Description of memories in Verilog
+* [[DIC Seminar 5]] - Description of memories in Verilog
-* [[CID Seminar 6]] - Finite automata
+* [[DIC Seminar 6]] - Finite automata
 You can dowload the programs used on the Altera website:
 https://dl.altera.com/13.0sp1/?edition=web