RAM Memory - Revizia istoricului

Cbira la 12 aprilie 2018 08:54

2018-04-12T08:54:13Z

Cbira: /* Implementing a RAM */

2018-04-12T08:00:19Z

Implementing a RAM

Cbira: /* Implementing a RAM */

2018-04-12T07:58:30Z

Implementing a RAM

Cbira: /* Implementing a RAM */

2018-04-12T07:57:58Z

Implementing a RAM

Cbira: Pagină nouă: [http://en.wikipedia.org/wiki/Random-access_memory Random Access Memory] are memory circuits. The difference between these and the ROM memories is that RAMs can also write, not jus...

2018-04-12T07:57:40Z

Pagină nouă: [http://en.wikipedia.org/wiki/Random-access_memory Random Access Memory] are memory circuits. The difference between these and the ROM memories is that RAMs can also write, not jus...

Pagină nouă

[http://en.wikipedia.org/wiki/Random-access_memory Random Access Memory] are memory circuits. The difference between these and the ROM memories is that RAMs can also write, not just read. Thus, besides the important parameters we know from ROM (the number of memory locations and the size of a location), a RAM can have one or more ports. These ports consist of multiple inputs and /or outputs, and can be of three types:
* write port - this port can only write to memory;
* Read port - read only memory from this port;
* read-write port - this port can also write and read, but only at the same address.

The read ports can also be of two types:
* asynchronous - if the data output changes asynchronously with changing the read address, and this output is wire type;
* synchronous - if the data output changes synchronously with the clock, regardless of the time of the change of address, and this output is reg.

The more memory a memory has, the higher (as area) and the slower it is. It is therefore recommended that a designer takes into account the functionality required for a memory and adds exactly the number and type of ports that are needed. For example, two read ports will not be added unless it is essential to read two memory locations at the same time.

'''Note:''' Each distinct port must have its own address entry.

== Interface of a RAM ==

The interface of a RAM contains the clock signal as an input. In addition, each port has the following signals:
* Read ports contain (as with a ROM where read only):
** location address as input
** data read from memory as output
* Writing ports contain:
** Destination address as input
** date to be written, also as entry
** A one-bit input signal commanding the input date write to the specified address, called the Write Enable (or '''we''').
* read-write ports contain:
** address of the location to be accessed (read or written) as input
** date to be written, also as entry
** data read from memory as output
** A one-bit input signal commanding the input date write to the specified address, called the Write Enable (or '''we''').

Outputs can be either wire type, for asynchronous ports, or reg for synchronous ports.

'''Warning:''' A RAM does not have a reset signal!

== Implementing a RAM ==

The memory cells of a RAM are defined as a register vector. Thus, a RAM of 1024 32-bit locations is defined inside the Verilog module as follows:

<syntaxhighlight lang="Verilog">
reg [31: 0] memory [0: 1023];
<syntaxhighlight>

This syntax expresses a vector of 1024 elements (0-1023), which elements are 32-bit registers (31-0). Access to one of the registers in the 1024 registers vector is done using the operator '''[]'''. For example, the register specified by an '''addr''' is accessed as follows:

<syntaxhighlight lang="Verilog">
Memory [addr]
<syntaxhighlight>

The rule: </font> Always write a memory location is synchronous (on the clock front), so it is done using a block always sequentially. </font> <font color="red" </div>

</font>> Always, reading a memory location on a synchronous port is always done using a block always sequential. </div> <div class="rule"

Rule: </font> Always read a memory location on an asynchronous port using an assign or always combinatorial block (assign is recommended). </font> <font color="red"> </div>

@@ Linia 46: / Linia 46: @@
 </syntaxhighlight>
-The rule: </font> Always write a memory location is synchronous (on the clock front), so it is done using a block always sequentially. </font> <font color="red" </div>
+<div class="regula"><font color="red">Rule:</font> Always write a memory location is synchronous (on the clock front), so it is done using a block always sequentially.</div>
-</font> Always, reading a memory location on a synchronous port is always done using a block always sequential. </div> <div class="rule"
+<div class="regula"><font color="red">Rule:</font> Always, reading a memory location on a synchronous port is always done using a block always sequential.</div>
-Rule: </font> Always read a memory location on an asynchronous port using an assign or always combinatorial block (assign is recommended). </font> <font color="red"> </div>
+<div class="regula"><font color="red">Rule:</font> Always read a memory location on an asynchronous port using an assign or always combinatorial block (assign is recommended). </div>

@@ Linia 1: / Linia 1: @@
 [http://en.wikipedia.org/wiki/Random-access_memory Random Access Memory] are memory circuits. The difference between these and the ROM memories is that RAMs can also write, not just read. Thus, besides the important parameters we know from ROM (the number of memory locations and the size of a location), a RAM can have one or more ports. These ports consist of multiple inputs and /or outputs, and can be of three types:
 * write port - this port can only write to memory;
-* Read port - read only memory from this port;
+* read port - read only memory from this port;
 * read-write port - this port can also write and read, but only at the same address.

@@ Linia 43: / Linia 43: @@
 <syntaxhighlight lang="Verilog">
-Memory [addr]
+memory[addr]
 </syntaxhighlight>
 The rule: </font> Always write a memory location is synchronous (on the clock front), so it is done using a block always sequentially. </font> <font color="red" </div>
-</font>> Always, reading a memory location on a synchronous port is always done using a block always sequential. </div> <div class="rule"
+</font> Always, reading a memory location on a synchronous port is always done using a block always sequential. </div> <div class="rule"
 Rule: </font> Always read a memory location on an asynchronous port using an assign or always combinatorial block (assign is recommended). </font> <font color="red"> </div>