Verilog EN - Revizia istoricului

Cbira: /* Concatenation operator */

2018-05-30T10:54:31Z

Concatenation operator

Cbira: /* Operators */

2018-05-30T10:36:15Z

Operators

Cbira: /* Operators */

2018-05-30T10:30:40Z

Operators

Cbira: /* Arithmetic Operators */

2018-05-30T10:21:18Z

Arithmetic Operators

Cbira: /* Clock signal in test modules */

2018-05-30T10:20:01Z

Clock signal in test modules

Cbira: /* Clock signal in test modules */

2018-05-30T10:19:34Z

Clock signal in test modules

Cbira: /* Instantiation blocks */

2018-05-30T10:16:52Z

Instantiation blocks

Cbira: /* Instantiation blocks */

2018-05-30T10:15:03Z

Instantiation blocks

Cbira: /* always sequential blocks. Non-blocking assignments */

2018-05-30T10:14:03Z

always sequential blocks. Non-blocking assignments

Cbira: /* always sequential blocks. Non-blocking assignments */

2018-05-30T10:12:47Z

always sequential blocks. Non-blocking assignments

@@ Linia 538: / Linia 538: @@
 ==== Concatenation operator ====
-The concatenation operator is "{" and "}". Thus, a series of semicolon-separated and closed signals between two braces will result in a single signal of size equal to the sum of the dimensions of the component signals.
+The concatenation operator is '{' and '}'. Thus, a series of semicolon-separated and closed signals between two braces will result in a single signal of size equal to the sum of the dimensions of the component signals.
 <syntaxhighlight lang="Verilog">

@@ Linia 525: / Linia 525: @@
 ==== Bit access operator ====
-Given a n-bit signal, the access operator to a signal bit sub-sequence is '''[m: k]''' where m and k are indexes of the desired bits with n <m <k. For example:
+Given a n-bit signal, the access operator to a signal bit sub-sequence is '''[m: k]''' where m and k are indexes of the desired bits with n < m < k. For example:
 <syntaxhighlight lang="verilog">
-reg [31: 0] un_register;
+reg [31: 0] a_register;
-wire [7: 0] un_fir;
+wire [7: 0] a_wire;
-wire alt_fir;
+wire another_wire;
-assign un_fir=unregister [30:23]; //the thread "un_fir" takes the value of the bit sequence from 23 to 30 in the register "un_register"
+assign a_wire = a_register [30:23]; //the wire "a_wire" takes the value of the bit sequence from 23 to 30 in the register "a_register"
-assign alt_fir=un_fir [3]; //the "alt_fir" thread will take the bit 3 value of the "one_fir" signal that is the bit 26 of the "one_register"
+assign another_wire = a_wire [3]; //the "another_wire" wire will take the bit 3 value of the "a_wire" signal that is the bit 26 of the "a_register"
 </syntaxhighlight>

@@ Linia 457: / Linia 457: @@
 |Addition || + || a + b
 |- bgcolor="#ddffdd" align="center"
-|Decrease || - || a - b
+|Substraction || - || a - b
 |- bgcolor="#ddffdd" align="center"
 |Multiplication || * || a * b
 |- bgcolor="#ddffdd" align="center"
-|Sharing || /|| a /b
+|Division || /|| a /b
 |}
@@ Linia 470: / Linia 470: @@
 |'''Operation''' || '''Operator''' || '''Example'''
 |- bgcolor="#ddffdd" align="center"
-|Equal || == || a == b
+|Equality || == || a == b
 |- bgcolor="#ddffdd" align="center"
-Different || !=|| a!=b
+|Non-equality || !=|| a!=b
 |- bgcolor="#ddffdd" align="center"
 |Less || <|| a <b
 |- bgcolor="#ddffdd" align="center"
-Less or equal || <= || a <= b
+|Less or equal || <= || a <= b
 |- bgcolor="#ddffdd" align="center"
-|Higher || > || a> b
+|More || > || a> b
 |- bgcolor="#ddffdd" align="center"
-|Higher or equal || >=|| a>=b
+|More or equal || >=|| a>=b
 |}
@@ Linia 493: / Linia 493: @@
 |Or || <nowiki> | </nowiki> || and <nowiki> | </nowiki> b
 |- bgcolor="#ddffdd" align="center"
-Exclusively || ^ || a ^ b
+|Exclusive or || ^ || a ^ b
 |}
@@ Linia 503: / Linia 503: @@
 |'''Operation''' || '''Operator''' || '''Example'''
 |- bgcolor="#ddffdd" align="center"
-|Deny || ~ || ~ b
+|Negation || ~ || ~ b
 |- bgcolor="#ddffdd" align="center"
-And the bits of a signal || & || & a
+|And the bits of a signal|| & || & a
 |- bgcolor="#ddffdd" align="center"
-Or the bits of a signal || <nowiki> | </nowiki> || <Nowiki> | </nowiki> a
+|Or the bits of a signal || <nowiki> | </nowiki> || <Nowiki> | </nowiki> a
 |- bgcolor="#ddffdd" align="center"
-Or exclusively on the bits of a signal || ^ || ^ a
+|Or exclusively on the bits of a signal || ^ || ^ a
 |}
@@ Linia 518: / Linia 518: @@
 |'''Operation''' || '''Operator''' || '''Example'''
 |- bgcolor="#ddffdd" align="center"
-Left Shift || << || a << b
+|Left Shift || << || a << b
 |- bgcolor="#ddffdd" align="center"
-Right Arrow || >> || a >> b
+|Right Shift || >> || a >> b
 |}
@@ Linia 554: / Linia 554: @@
 ==== Replication operator ====
-The replication operator is used when it is desired to replicate a large or unknown number of times (given as a parameter). Thus, the construction '''{n {m}}''' represents the signal '''' m '''multiplied by' 'n''' times.
+The replication operator is used when it is desired to replicate a large or unknown number of times (given as a parameter). Thus, the construction '''{n {m}}''' represents the signal '''m''' multiplied by '''n''' times.
 <syntaxhighlight lang="Verilog">

@@ Linia 455: / Linia 455: @@
 |'''Operation''' || '''Operator''' || '''Example'''
 |- bgcolor="#ddffdd" align="center"
-Assembly || + || a + b
+|Addition || + || a + b
 |- bgcolor="#ddffdd" align="center"
 |Decrease || - || a - b

@@ Linia 434: / Linia 434: @@
 initial begin
      clock=0;
-     forever #1 clock =! clock;
+     forever #1 clock = ~clock;
 end
 </syntaxhighlight>

@@ Linia 428: / Linia 428: @@
 === Clock signal in test modules ===
-The keyword '''' forever '''is used to execute a assignment or function call repeatedly until the end of the simulation. This is particularly useful for generating a clock signal. The next sequence of code generates a clock signal with two time units:
+The keyword ''' forever ''' is used to execute a assignment or function call repeatedly until the end of the simulation. This is particularly useful for generating a clock signal. The next sequence of code generates a clock signal with two time units:
 <syntaxhighlight lang="Verilog">
 reg clock;
@@ Linia 439: / Linia 439: @@
-For the sequential circuits, the test module will have two '''' initial '''blocks. </font> </font> The first is similar to the one above, and used to generate the clock signal. The second is used to generate the other input signals and the simulation stop directive. The reason for this segregation is that the instruction '''' 'forever''' is blocking (that is, the instructions given after it are not executed). All of the '''' initial '' blocks in a test module run in parallel. </div>
+<div class="regula"><font color="red">Rule:</font> For the sequential circuits, the test module will have two '''initial''' blocks. The first is similar to the one above, and used to generate the clock signal. The second is used to generate the other input signals and the simulation stop directive. The reason for this segregation is that the instruction '''forever''' is blocking (that is, the instructions given after it are not executed). All of the '''' initial ''' blocks in a test module run in parallel. </div>
 == Verilog syntax ==

@@ Linia 317: / Linia 317: @@
 );
-//define the binding yarns
+//define the connecting wires
 wire [3: 0] subsum0;
 wire [3: 0] subsum1;
@@ Linia 326: / Linia 326: @@
      .in0 (in0), //at the input called in0 of the adder0 instance, the input in0 of the module
      .in1 (in1) //at the input called in1 of the adder0 instance connects the input in1 of the module
+);
 Adder adder1 (
@@ Linia 332: / Linia 332: @@
      .in0 (in2), //at the input called in0 of the adder1 instance, the in2 input of the module
      .in1 (in3) //at the input called in1 of the adder1 instance it binds the input in3 of the module
+);
 Adder adder2 (
@@ Linia 338: / Linia 338: @@
      .in0 (subsum0), //at the input called in0 of the adder2 instance, the thread subsum0
      .in1 (subsum1) //at the input called in1 of the adder2 instance, the thread subsum1
+);
 endmodule
@@ Linia 363: / Linia 363: @@
      .in0 ({1'b0, in0}), //at the input called in0 of the adder0 instance binds a bit 0 concatenated with the input in0 of the module
      .in1 ({1'b0, in1}) //at the input called in1 of the adder0 instance binds a 0 bit concatenated with the in1 input of the module
+);
 Adder adder1 (
@@ Linia 369: / Linia 369: @@
      .in0 ({1'b0, in2}), //at the input called in0 of the adder1 instance binds a bit 0 concatenated with the input in2 of the module
      .in1 ({1'b0, in3}) //at the input called in1 of the adder1 instance, a bit 0 concatenated with the input of the module
+);
 Adder adder2 (
@@ Linia 375: / Linia 375: @@
      .in0 (subsum0 [3: 0]), //at the input called in0 of the adder2 instance, the least significant 4 bits of the submodule thread
      .in1 (subsum1 [3: 0]) //At the input called in1 of the adder2 instance, the least significant 4 bits of the submode thread 1
+);
 endmodule

@@ Linia 304: / Linia 304: @@
      //...
      .nume_intrare_sau_iesire_n (nume_semnal_legat_la_intrare_sau_iesire_n)
+);
 </syntaxhighlight>
@@ Linia 315: / Linia 315: @@
      input [2: 0] in2,
      input [2: 0] in3
+);
 //define the binding yarns
@@ Linia 352: / Linia 352: @@
      input [2: 0] in2,
      input [2: 0] in3,
+);
 //define the binding yarns

@@ Linia 282: / Linia 282: @@
 <div class="rule">
-<font color="red"> '''''' Rule: '''' '</font> In the same block''' always''', the same type of assignment operator is used for all operations.
+<font color="red"> ''''' Rule: '''''</font> In the same block''' always''', the same type of assignment operator is used for all operations.
 </div>

@@ Linia 207: / Linia 207: @@
      input [3: 0] in1,
      input clock
+);
 //implementation here
@@ Linia 227: / Linia 227: @@
      input [3: 0] in1,
      input clock
+);
 always @ (posedge clock) begin
@@ Linia 243: / Linia 243: @@
 module RegSwapper (
      //...
+);
 reg [31: 0] reg0;
@@ Linia 262: / Linia 262: @@
 module RegSwapper (
      //...
+);
 reg [31: 0] reg0;