Xilinx Platform Studio - Revizia istoricului

Lpetrica: /* Exporting to SDK */

2012-11-17T13:01:04Z

Exporting to SDK

Lpetrica: /* Exporting to SDK */

2012-11-17T13:00:16Z

Exporting to SDK

Lpetrica la 17 noiembrie 2012 12:59

2012-11-17T12:59:29Z

Lpetrica: /* Adding Peripherals to the System */

2012-11-17T11:34:10Z

Adding Peripherals to the System

Lpetrica: /* Adding Peripherals to the System */

2012-11-17T11:30:14Z

Adding Peripherals to the System

Lpetrica: /* Base System Builder */

2012-11-17T11:24:18Z

Base System Builder

Lpetrica: /* Generating Peripherals */

2012-11-17T10:27:11Z

Generating Peripherals

Lpetrica: /* Generating Peripherals */

2012-11-17T10:19:48Z

Generating Peripherals

Lpetrica la 17 noiembrie 2012 10:17

2012-11-17T10:17:50Z

Lpetrica la 16 noiembrie 2012 21:42

2012-11-16T21:42:25Z

← Versiunea anterioară		Versiunea de la data 17 noiembrie 2012 13:01
Linia 115:		Linia 115:
	[[Fișier:XPSExportSDK.png]]		[[Fișier:XPSExportSDK.png]]

−	Select to export the bitfile along with the project, and click on '''Export ~~and Start~~ SDK'''. This will process the project into a form which is understandable by SDK and will then launch SDK with your hardware project loaded, and ready to create software applications.	+	Select to export the bitfile along with the project, and click on '''Export & Launch SDK'''. This will process the project into a form which is understandable by SDK and will then launch SDK with your hardware project loaded, and ready to create software applications.

@@ Linia 113: / Linia 113: @@
 In the '''Navigator''' panel, notice the '''Export to SDK''' option. After the project is configured and you have generated a bitfile, click this button to export the project to Xilinx SDK. A pop-up window will appear with the following contents:
-[[Fișier:XPSExportSDK.jpg]]
+[[Fișier:XPSExportSDK.png]]
 Select to export the bitfile along with the project, and click on '''Export and Start SDK'''. This will process the project into a form which is understandable by SDK and will then launch SDK with your hardware project loaded, and ready to create software applications.

← Versiunea anterioară		Versiunea de la data 17 noiembrie 2012 12:59
Linia 108:		Linia 108:
	[[Fișier:XPSAddIP4.png\|400px]]		[[Fișier:XPSAddIP4.png\|400px]]
	[[Fișier:XPSAddIP5.png\|500px]]		[[Fișier:XPSAddIP5.png\|500px]]
		+
		+	== Exporting to SDK ==
		+
		+	In the '''Navigator''' panel, notice the '''Export to SDK''' option. After the project is configured and you have generated a bitfile, click this button to export the project to Xilinx SDK. A pop-up window will appear with the following contents:
		+
		+	[[Fișier:XPSExportSDK.jpg]]
		+
		+	Select to export the bitfile along with the project, and click on '''Export and Start SDK'''. This will process the project into a form which is understandable by SDK and will then launch SDK with your hardware project loaded, and ready to create software applications.

@@ Linia 97: / Linia 97: @@
 We will now integrate the peripheral generated in the previous section to our system. The first step is to look for the peripheral in the IP Catalog and add it to the peripheral list. Select '''Add IP''' from the right-click menu and click '''OK''' in the pop-up window which follows.
-[[Fișier:XPSAddIP1.png]]
+[[Fișier:XPSAddIP1.png|400px]]
-Next, we must connect the peripheral to the PLB bus by selecting '''mb_plb''' in the bus drop-down menu. This will connect the peripheral to the main PLB bus and add an unmapped address space in the '''Addresses''' tab. From '''Addresses''' select 64KB as the memory space size and click on '''Generate Addresses''' in the top-right corner in order for the system address map to be recalculated
+Next, we must connect the peripheral to the PLB bus by selecting '''mb_plb''' in the bus drop-down menu. This will connect the peripheral to the main PLB bus and add an unmapped address space in the '''Addresses''' tab. From '''Addresses''' select 64KB as the memory space size.
-[[Fișier:XPSAddIP2.png]]
+[[Fișier:XPSAddIP2.png|400px]]
-[[Fișier:XPSAddIP3.png]]
+[[Fișier:XPSAddIP3.png|500px]]
-If successful, the '''Console''' window will show the new address map, and the '''Addresses''' tab will also be updated with the new address map.
+Next, click on '''Generate Addresses''' in the top-right corner in order for the system address map to be recalculated. If successful, the '''Console''' window will show the new address map, and the '''Addresses''' tab will also be updated with the new address map.
-[[Fișier:XPSAddIP5.png]]
+[[Fișier:XPSAddIP4.png|400px]]

← Versiunea anterioară		Versiunea de la data 17 noiembrie 2012 11:30
Linia 94:		Linia 94:

	== Adding Peripherals to the System ==		== Adding Peripherals to the System ==
		+
		+	We will now integrate the peripheral generated in the previous section to our system. The first step is to look for the peripheral in the IP Catalog and add it to the peripheral list. Select '''Add IP''' from the right-click menu and click '''OK''' in the pop-up window which follows.
		+
		+	[[Fișier:XPSAddIP1.png]]
		+
		+	Next, we must connect the peripheral to the PLB bus by selecting '''mb_plb''' in the bus drop-down menu. This will connect the peripheral to the main PLB bus and add an unmapped address space in the '''Addresses''' tab. From '''Addresses''' select 64KB as the memory space size and click on '''Generate Addresses''' in the top-right corner in order for the system address map to be recalculated
		+
		+	[[Fișier:XPSAddIP2.png]]
		+	[[Fișier:XPSAddIP3.png]]
		+	[[Fișier:XPSAddIP4.png]]
		+
		+	If successful, the '''Console''' window will show the new address map, and the '''Addresses''' tab will also be updated with the new address map.
		+
		+	[[Fișier:XPSAddIP5.png]]

@@ Linia 21: / Linia 21: @@
 In the ''System'' window, select to create a single-processor system.
-In the ''Processor'' window, select the '''Microblaze''' processor and '''50 Mhz''' from the frequency drop-down menu. Change the '''Local Memory''' selection to 16KB or more from the default 8KB if you intend to implement more complex software projects on the hardware platform. Also, the user may choose to add hardware floating-point support to the Microblaze processor. For this tutorial, the local memory will be set at 16KB, and hardware floating-point will be disabled.
+In the ''Processor'' window, select the '''Microblaze''' processor and '''50 Mhz''' from the frequency drop-down menu. Change the '''Local Memory''' selection to 16KB or more from the default 8KB if you intend to implement more complex software projects on the hardware platform. Also, the user may choose to add hardware floating-point support to the Microblaze processor. For this tutorial, the local memory will be set at 8KB, and hardware floating-point will be disabled.
 [[Fișier:BSBWizard5.png|500px]]

@@ Linia 69: / Linia 69: @@
 In the ''Name and Version'' window, give your peripheral a name, a version number and a description. In this example we will use the name '''first_peripheral''' and the default version number
-[[Fișier:XPSperiph1.png]]
+[[Fișier:XPSperiph1.png|300px]]
 The following window allows the user to select which type of bus the peripheral will use for its connection to the system processor. Select '''PLB''' to generate a peripheral which is compatible with the example XPS project used in this tutorial. The lower part of the wizard window shows links to relevant documentation about the selected bus.
-[[Fișier:XPSPeriph2.png]]
+[[Fișier:XPSPeriph2.png|300px]]
 The '''IPIF Services''' window allows the user to configure the interface of the peripheral with the bus. The user can enable the generation of various interface circuitry. Enable the software register, the read/write FIFOs, the user logic software register and the data phase timer.
-[[Fișier:XPSPeriph3.png]]
+[[Fișier:XPSPeriph3.png|500px]]
 In the '''Slave Interface''' window, just click '''Next'''. The following window configures the '''FIFO Service'''. Because we have selected to add read/write FIFOs to the bus interface, we can configure the parameters of these FIFOs. Deselect '''Packet Mode''' for both the Write FIFO and the Read FIFO. Please note that Read and Write is from the perspective of the system processor. Detailed information about the FIFO circuitry can be accessed by clicking on the '''Datasheet''' button corresponding to each FIFO.
-[[Fișier:XPSPeriph4.png]]
+[[Fișier:XPSPeriph4.png|500px]]
 The '''User SW Register''' window allows the user to select the number of software-accesible registers generated. Specify to select 8 registers, and click '''Next'''. Do the same in the following two windows, which will bring you to the '''Peripheral Implementation Support''' window. Enable '''Generate stub user_logic template in Verilog instead of VHDL'''. Click '''OK''' in the resulting warning pop-up window. Click '''Next''' to go to the final wizard screen.
@@ Linia 87: / Linia 87: @@
 In the '''Congradulations''' window you are shown the final settings for the configured peripheral. Please note the generated address space, which shows offsets from the peripheral base address for software registers, the reset register and the fifo interfaces.
-[[Fișier:XPSPeriph5.png]]
+[[Fișier:XPSPeriph5.png|500px]]
 Click '''Finish''' to generate your peripheral. It will be stored in the project folder, under the subfolder '''pcores/first_peripheral'''. Under '''first_peripheral/hdl/verilog''' you will find a Verilog file called '''user_logic.v''' which contains example logic for the software register interface, and all signals required to work with the FIFO interfaces.
 == Adding Peripherals to the System ==

← Versiunea anterioară		Versiunea de la data 17 noiembrie 2012 10:17
Linia 60:		Linia 60:

	== Generating Peripherals ==		== Generating Peripherals ==
		+
		+	XPS allows the user to generate custom peripherals. In order to do this, go to '''Hardware -> Create or Import Peripheral''', which will start the peripheral creation wizard.
		+
		+	In the first welcome screen, click '''Next'''. In the next window, select '''Create templates for a new peripheral''', then click '''Next'''.
		+
		+	In the ''Repository or Project'' window, select to store the peripheral to an XPS project. The default setting is to store the peripheral to the project which was open when the wizard was started in XPS.
		+
		+	In the ''Name and Version'' window, give your peripheral a name, a version number and a description. In this example we will use the name '''first_peripheral''' and the default version number
		+
		+	[[Fișier:XPSperiph1.jpg]]
		+
		+	The following window allows the user to select which type of bus the peripheral will use for its connection to the system processor. Select '''PLB''' to generate a peripheral which is compatible with the example XPS project used in this tutorial. The lower part of the wizard window shows links to relevant documentation about the selected bus.
		+
		+	[[Fișier:XPSPeriph2.jpg]]
		+
		+	The '''IPIF Services''' window allows the user to configure the interface of the peripheral with the bus. The user can enable the generation of various interface circuitry. Enable the software register, the read/write FIFOs, the user logic software register and the data phase timer.
		+
		+	[[Fișier:XPSPeriph3.png]]
		+
		+	In the '''Slave Interface''' window, just click '''Next'''. The following window configures the '''FIFO Service'''. Because we have selected to add read/write FIFOs to the bus interface, we can configure the parameters of these FIFOs. Deselect '''Packet Mode''' for both the Write FIFO and the Read FIFO. Please note that Read and Write is from the perspective of the system processor. Detailed information about the FIFO circuitry can be accessed by clicking on the '''Datasheet''' button corresponding to each FIFO.
		+
		+	[[Fișier:XPSPeriph4.png]]
		+
		+	The '''User SW Register''' window allows the user to select the number of software-accesible registers generated. Specify to select 8 registers, and click '''Next'''. Do the same in the following two windows, which will bring you to the '''Peripheral Implementation Support''' window. Enable '''Generate stub user_logic template in Verilog instead of VHDL'''. Click '''OK''' in the resulting warning pop-up window. Click '''Next''' to go to the final wizard screen.
		+
		+	In the '''Congradulations''' window you are shown the final settings for the configured peripheral. Please note the generated address space, which shows offsets from the peripheral base address for software registers, the reset register and the fifo interfaces.
		+
		+	[[Fișier:XPSPeriph5.png]]
		+
		+	Click '''Finish''' to generate your peripheral. It will be stored in the project folder, under the subfolder '''pcores/first_peripheral'''. Under '''first_peripheral/hdl/verilog''' you will find a Verilog file called '''user_logic.v''' which contains example logic for the software register interface, and all signals required to work with the FIFO interfaces.

	== Adding Peripherals to the System ==		== Adding Peripherals to the System ==

@@ Linia 43: / Linia 43: @@
 The '''IP Catalog''' is a database of pre-designed peripherals and accelerator cores supplied by Xilinx as part of the ISE System Edition software package. Right-clicking on any item in the catalog will enable the user to add the item to the hardware system. The new system will need to be connected and mapped in the address space of the processor. Co-located with the IP Catalog is the '''Project''' tab, which shows information on file location, target FPGA and other project properties.
-[[Fișier:IPCatalog.png]][[Fișier:XPSProject.png]]
+[[Fișier:IPCatalog.png]]
 The '''System Assembly''' panel contains three tabs: '''Bus Interfaces''', '''Ports''' and '''Addresses'''.
@@ Linia 49: / Linia 50: @@
 The '''Bus Interfaces''' tab allows components to be connected and disconnected from system busses and the bus layout to be viewed in graphical form.
-[[Fișier:XPSBusInterfaces.png]][[Fișier:XPSPorts.png]]
+The '''Ports''' tab allows connection of IO signals between components and FPGA pins, but can also be used to connect components with each-other or to connect global signals like clock and reset to individual system components.
-The '''Ports''' tab allows connection of IO signals between components and FPGA pins, but can also be used to connect components with each-other or to connect global signals like clock and reset to individual system components.
+[[Fișier:XPSBusInterfaces.png|500px]]
 The '''Addresses''' tab shows the processor address map split into regions corresponding to each peripheral. The amount of memory allocated to each peripheral is configurable. Peripheral address spaces can also be locked.
-[[Fișier:XPSAddresses.png]]
+[[Fișier:XPSAddresses.png|700px]]