Advanced FPGA Design

Overview

The Advanced FPGA Design course covers topics related to the efficient implementation of digital circuits on FPGA devices, including combinatorial and sequential logic, memory, high-speed arithmetic, clocking and IOs.

Grading

Points will be awarded for the following activities:

• 25 points for 5 homework assigments in weeks 2-6
• 50 points for a System-on-Chip project in weeks 7-11
• 25 points for final exam (multiple choice test)

Course Material

Slides will be uploaded as they are presented in class.

Fișier:FPGA Intro.pdf

Fișier:FPGA Logic.pdf

Fișier:FPGA SRL DistRAM.pdf

Fișier:FPGA BlockRAM.pdf

Fișier:FPGA DSP.pdf

Fișier:FPGA Clocking.pdf

Fișier:FPGA SERDES.pdf

Tutorials

The following tutorials demonstrate the use of XPS and SDK in creating hardware platforms for Xilinx FPGAs and developing software for these platforms.

1. Xilinx Platform Studio
2. Software Development Kit

Homework Assignments

Assignments will be issued during the class and the deadline is the beginning of the next week's class. Homework assigments will be submitted via email, with the subject AM_FPGA_HWn where n is the number of the assignment. Attach all source code and other materials required for grading.

The following assignments have been presented:

• Assignment 1 - implement a 16-bit population count circuit which outputs the number of '1' bits of the 16-bit input number. Implement this circuit with ripple carry adders (RCA) and note synthesis results: resource utilization and estimated delay. Implement the same circuit utilizing carry save adders (CSA) and compare synthesis results to the RCA implementation.

• Assignment 2 - implement a synchronous FIFO utilizing SRL (LUT shift registers) for data storage. The FIFO is 16 bits wide. Implement the FIFO and evaluate resource utilization and top frequency for depths from 4 to 64 bits. The FIFO will be reset through the GSR.

• Assignment 3 - implement an 8-bit population count as a Block RAM. Define a read-only RAM port and utilize the RAM initialization procedure to make sure the memory is initialized at configuration time. The implementation will target the Xilinx Virtex-6 architecture.

• Bonus Assignment - implement an instruction decoder (to be provided as source code) fully in Block RAM, targeting the Xilinx Zynq architecture. 10 points will be awarded for this assignment, and the deadline is the end of the semester. Please ask for the decoder source code by e-mail if interested.

• Assignment 4 - implement for the Virtex-6 architecture a complex number multiplier C=A*B where A and B have 18-bit, signed values for their real and imaginary parts. The circuit should utilize DSP48 slices as much as possible. Report the resource utilization and maximum frequency.

• Assignment 5 is canceled, 5 points will be added by default to the grade of each student

Name	HW1	HW2	HW3	HW4
Balaban Valeriu	4	0	0	0
Catrina Andrei	5	5	5	5
Gheolbanoiu Alexandru	5	4	5	5
Grigoras Gabriel	5	0	5	5
Mocanu Dan	4	4	5	4
Popescu Vlad	2	5	5	5
Prajinariu Sebastian	2	5	0	5
Rusu Andrei	5	5	5	5
Stanculescu Sergiu	5	4	5	5
Yang Haining	5	3	2	3

Projects

Fișier:FPGA Projects 2014-2015.pdf

The project assignments will be implemented as a Xilinx XPS/SDK project, with a Microblaze processor for control and user communication through RS232. Students may utilize all peripherals available to them in Xilinx SDK for the Nexys 2 board (memory, RS232 interface). A custom peripheral will be generated in Xilinx XPS for the video processing elements of each project assignment.

Project allocation is listed in the following table:

Project Number	Student(s)
1	Alexandru Gheolbanoiu, Aurelian Ioan
2	Sebastian Prajinariu
3	Alexandra Spataru, Dan Mocanu
4	Valeriu Balaban
5	Andrei Catrina
6	Vlad Georgescu
7	Sergiu Stanculescu
8	Vlad Popescu, Laurentiu Ilie
9	Haining Yang, Andrei Rusu