Quartus II tutorial

Programming the experimental board DE1 with Quartus II (version 13.0sp1)

Example: synthesis of a 4-bit sumer.

To open the Quartus II application you can use:

- the shortcut on the screen

- the executable file in the installation location

- the program menu

steps:

=1. Create a project When we open the Quartus II program a welcome screen appears, where we have the option "Create new project". If we do not see this window, select "New Project Wizard" from the File menu, or select File - New and then "New Quartus II Project"). In both cases, the Wizard will open to help us set the settings for the new project. If you defend an input screen, click Next (we can check "Do not show this introduction again" to skip this step in the future).

1.1. Project name and location

First step: setting the project directory (working directory) and project name. The project will be saved in a new directory created by us in the /home /student directory. The project must have a name, which is usually the same as the top-level design entity (which automatically completes when writing the name of the project). If there are other Quartus II projects in the project location, a warning screen appears. The project in this tutorial is called Adder and the top-level design entity is also called Adder. You will use appropriate names for the project you are implementing.

1.2. Adding Files

If we use files we have written in our project, we can add them from the beginning to the project in this window. If you do not want to add files already created to your project, you can click Next to go to the next step. You can add files to the project and then to the Settings menu.

1.3. Device selection

In the next step (the third screen in the wizard) select the device to be used for deployment. Select Cyclone II to Device Family. From the list of specific devices select EP2C20F484C7. (La Target device must be selected "Specific device selected in Available devices list" option). Then tap Next to go to the next step.

1.4. Simulator Selection

On page 4 of the wizard we will mention other programs that we use in design (for synthesis, simulation, verification). For example, if we want to use ModelSim, we select Simulation ModelSim for Verilog HDL. We can also rely on the Quartus II software and go through this step by tapping Next.

After clicking the Next button, you will see the last window in the New Project Wizard where a summary of the choices you have chosen for creating the project is displayed. After clicking the Finish button, the project will be created.

2. Source file design (top-level design entity)

The top-level design entity is a Verilog file or schema.

If you have already written the files and added them with Add Files, go to the next step. If you want to add files to this stage (and you have not added them before), use the Assignments -> Settings menu to add files and then go to the next step.

Here's how to use the Quartus II text editor.

Implementation example: We will implement a 4-bit binary number adder, which will be called Adder.v.

Caution! The top-level module must have the previously specified name when the project was created.

To use the Quartus II editor, select File -> New.

A window will open in which you will select Verilog HDL File, press OK. The text editor opens.

Select File -> Save As to choose the file name. In the window that appears, you will write the name of the file - for the top level design entity you have previously chosen - and select "Add file to current project". Tap Save. The file will be saved in the project directory.

Enter the editor and continue writing the Verilog code.

Example:

<syntaxhighlight lang="verilog">

module Adder (

output [4: 0] out,

input [3: 0] in0,

input [3: 0] in1);

assign out=in0 + in1;

endmodule

<syntaxhighlight>

Save the file using File -> Save or the Ctrl-s key combination. For more editor options, you can access Tools-> Options -> Text Editor.

3. Compiling

Select Start Compilation in the Processing menu or press the Start Compilation button (with the symbol commonly used for Play) and wait for the result of the compilation.

Ignore the Warning messages that appear during compilation - these are due to the fact that we have not fixed certain implementation parameters.

The possible errors in this phase are mainly Verilog syntax errors or errors due to the wrong name of the top-level module.

Use the Settings menu to correct the settings. For example, you can change the top-level design entity in the Assignments - Settings menu.

=4. Input /output pin configuration

Adding Pin Assignments

During compilation, the Quartus II compiler chooses the FPGA pins to which the inputs and outputs of our circuit will be connected. The DE1 board has connections already made between the FPGAs and other components on the board, so we can only use some pins according to these connections. For the inputs of the circuits we design, we can use the 10 switches and the buttons on the board. For exits we can use the 18 LEDs (10 red LEDs and 8 green LEDs) and the 7-segment display.

For example, we will link the input to0 to the SW0 - SW3 switches, the input1 to the SW4 - SW7 switches and the LEDR0 - LEDR4 LEDR4 output. Refer to the Pine Correction Board documentation table.

Pin Assignment is done using Assignment Editor or Pin Planner. Select Assignments -> Assignment Editor. A window will open like the one in the following picture:

In this editor, we need to write all the ports of the circuit and the pins we connect. It's simpler to do this association in Pin Planner, where we only have to modify the "Location" column. Note that changes made to Pin Planner are automatically saved in Assignment Editor.

DE1 has fixed pin assignments. Completing a design can help the user by using the same pin assignments for future projects. You can load a Pin Assignments file by selecting Assignments -> Import Assignments. (You can use the file with all pin assignments on the DE1 - DE1_pin_assignments.csv board, editing the names). Save Changes. After assigning the pins the result will look like in the image below:

Recompile using the Start Compilation button and wait for the compilation result.

=5. Board Programming

The programming stage of the FPGA board is as follows:

Start the board using the red button.

Caution: Make sure the board is on now (the power cord is plugged in, the USB cable is plugged in, the red button pressed, the RUN /PROG switch is in the RUN position).

Select Tools -> Programmer (or press the Programmer button) to get to the window in the following figure:

At the top, you must have selected USB-Blaster and JTAG mode.

If the USB-Blaster is not selected automatically, press the Hardware Setup button and select USB-Blaster in the window that appears.

If no file appears in the window, click the Add File button and select the Adder.sof file (This file is created by the compiler). Find it in the project folder in the Output Files folder.

Make sure the selected device is EP2C20F484 (at the bottom half of the screen).

You can now press the Start button and wait for the platen to be programmed. In the upper right corner of the window you have a progress indicator.

Errors at this stage may be due to the fact that you have not correctly set the device in the project (you can correct this wrong setting in the Assignments /Device menu.

After the programming has been completed, you can test the correct circuit operation using the SW0-SW7 Switches and observing the summation results on the red LEDR0-LEDR4 LEDs.