The Decoder
The decoder is a combinational circuit which is used to identify the specified input value by setting the output of the bit on the corresponding index to the input. The decoder is equivalent to a 1-bit multiplexer and the constant data input of 1.
For example, for a 4-bit decoder, the port table is shown below (the _ character can be used in Verilog to separate bits or numbers belonging to a base in writing a constant, for ease of reading; 16'b0100_0011_0100_0111)
| INPUT | OUTPUT |
| 0000 | 0000_0000_0000_0001 |
| 0001 | 0000_0000_0000_0010 |
| 0010 | 0000_0000_0000_0100 |
| 0011 | 0000_0000_0000_1000 |
| 0100 | 0000_0000_0001_0000 |
| 0101 | 0000_0000_0010_0000 |
| 0110 | 0000_0000_0100_0000 |
| 0111 | 0000_0000_1000_0000 |
| 1000 | 0000_0001_0000_0000 |
| 1001 | 0000_0010_0000_0000 |
| 1010 | 0000_0100_0000_0000 |
| 1011 | 0000_1000_0000_0000 |
| 1100 | 0001_0000_0000_0000 |
| 1101 | 0010_0000_0000_0000 |
| 1110 | 0100_0000_0000_0000 |
| 1111 | 1000_0000_0000_0000 |
Interface
The interface of a decoder is made up of two signals:
- input of n bits;
- output of 2 n bits.
Implementation
There are several possible implementations for the decoder:
- using blocks generate for;
- using blocks always combinational and case;
- using a block assign and the left shift operator.
Although the last variant is not optimal from the point of view of the synthesized circuit, we will use this method because of the ease and short dimension of the description.
