AES Encryption

Objective

Create a PLB peripheral for AES encryption and test attained acceleration when compared to a processor-only AES implementation.

References

http://en.wikipedia.org/wiki/Aes

Requirements

1. Implement a circuit for AES acceleration in Verilog (integrated within a user_logic.v peripheral template)
2. Implement a test-bench for the Verilog code
3. Analyze FPGA resource utilization of your circuit
4. Create an XPS system which uses the AES peripheral, implement the system and export it to SDK
5. Create a C code project for processor-only AES encryption and test speed
6. Create a C code project for accelerated AES encryption and test speed