Applications 6

Exercise 1

D flip-flop

the output takes the value of the input, q <= d, but only at discrete moments of time, when the control signal clk changes from 0 to 1, always @(posedge clk).

clock generation in testbench

initial begin
    clk = 0;                // initialization at time 0
    forever #5 clk = ~clk;  // toggle the clock at each 5 simulation steps
end

Exercise 2

8 bit D register

structural description with flip-flops