DIC Lab Work 4: Diferență între versiuni

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(Notions and Knowledge Required)
(Notions and Knowledge Required)
 
(Nu s-au afișat 12 versiuni intermediare efectuate de același utilizator)
Linia 1: Linia 1:
== Notions and Knowledge Required ==
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== Required Notions and Knowledge ==
  
* [[Introduction. Verilog HDL and ModelSim | Boolean logic and numbering systems]]
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* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]]
 
* Verilog Syntax [[Verilog_EN]]
 
* Verilog Syntax [[Verilog_EN]]
* [[Tutorial_Quartus_II | Using the Altera Quartus II Synthesis Program]]
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* [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]]
* [http://wiki.dcae.pub.ro/images/f/fc/Pini_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for plate DE1]
 
 
* [http://wiki.dcae.pub.ro/images/f/fc/Pinii_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for DE1 board], [http://wiki.dcae.pub.ro/images/3/37/Pin_Assignments_Cyclone_V_.pdf List of pins for DE1-SoC board]
 
* [http://wiki.dcae.pub.ro/images/f/fc/Pinii_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for DE1 board], [http://wiki.dcae.pub.ro/images/3/37/Pin_Assignments_Cyclone_V_.pdf List of pins for DE1-SoC board]
 
* [[Sequential Circuits]], [[Counter]]
 
* [[Sequential Circuits]], [[Counter]]
* [[Pulse generator with variable filling factor]]
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* [[Pulse generator with variable duty cycle]]
  
 
== Example ==
 
== Example ==
  
Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable fill factor signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator.
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Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable duty cycle signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator.
  
 
== Exercise ==
 
== Exercise ==
  
Build a circuit that instantiates 8 variable fill factor signal generators to form a LEDG7-LEDG0 intensity ramp with the following features:
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Build a circuit that instantiates 8 variable duty cycle signal generators to form a LEDG7-LEDG0 intensity ramp with the following features:
 
* LEDG0 intensity, denoted I <sub> LEDG0 </sub> is determined by SW7-SW0
 
* LEDG0 intensity, denoted I <sub> LEDG0 </sub> is determined by SW7-SW0
 
* The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships):
 
* The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships):
* #I <sub> LEDG0 </sub> &lt; I <sub> LEDG1 </sub> &lt; I <sub> LEDG2 </sub> &lt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &lt; I <sub> LEDG1 </sub> &lt; I <sub> LEDG2 </sub> &lt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
* #I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &lt; I <sub> LEDG2 </sub> &lt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &lt; I <sub> LEDG2 </sub> &lt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
* #I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &lt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &lt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
* #I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &lt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
* #I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &lt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
* #I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &gt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &gt; I <sub> LEDG5 </sub> &lt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
* #I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &gt; I <sub> LEDG5 </sub> &gt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &gt; I <sub> LEDG5 </sub> &gt; I <sub> LEDG6 </sub> &lt; I <sub> LEDG7 </sub>
* #I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &gt; I <sub> LEDG5 </sub> &gt; I <sub> LEDG6 </sub> &gt; I <sub> LEDG7 </sub>
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*#I <sub> LEDG0 </sub> &gt; I <sub> LEDG1 </sub> &gt; I <sub> LEDG2 </sub> &gt; I <sub> LEDG3 </sub> &gt; I <sub> LEDG4 </sub> &gt; I <sub> LEDG5 </sub> &gt; I <sub> LEDG6 </sub> &gt; I <sub> LEDG7 </sub>
  
 
== Bonus Exercise ==
 
== Bonus Exercise ==
  
Make a circuit that then turns off a led gradually, using a variable fill factor generator.
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Build a circuit that then turns off a led gradually, using a variable duty cycle generator.

Versiunea curentă din 30 mai 2018 09:32

Required Notions and Knowledge

Example

Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable duty cycle signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator.

Exercise

Build a circuit that instantiates 8 variable duty cycle signal generators to form a LEDG7-LEDG0 intensity ramp with the following features:

  • LEDG0 intensity, denoted I LEDG0 is determined by SW7-SW0
  • The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships):
    1. I LEDG0 < I LEDG1 < I LEDG2 < I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
    2. I LEDG0 > I LEDG1 < I LEDG2 < I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
    3. I LEDG0 > I LEDG1 > I LEDG2 < I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
    4. I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
    5. I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
    6. I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 > I LEDG5 < I LEDG6 < I LEDG7
    7. I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 > I LEDG5 > I LEDG6 < I LEDG7
    8. I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 > I LEDG5 > I LEDG6 > I LEDG7

Bonus Exercise

Build a circuit that then turns off a led gradually, using a variable duty cycle generator.