Digital Systems Design - Project: Diferență între versiuni
De la WikiLabs
Jump to navigationJump to search
Fără descriere a modificării |
Fără descriere a modificării |
||
| Linia 1: | Linia 1: | ||
== Design Specifications == | == Design Specifications == | ||
#Simple RISC ISA v.2.3 | # [http://wiki.dcae.pub.ro/images/e/e6/DSD_Project_RISC_ISA_v2_3.pdf Simple RISC ISA v.2.3] | ||
== Assignments == | == Assignments == | ||
#[http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model] | # [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model] | ||
Versiunea de la data 4 octombrie 2016 15:57
Design Specifications
Assignments
