Digital Systems Design - Project: Diferență între versiuni
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# [http://wiki.dcae.pub.ro/images/e/e6/DSD_Project_RISC_ISA_v2_3.pdf Simple RISC ISA v.2.3] | # [http://wiki.dcae.pub.ro/images/e/e6/DSD_Project_RISC_ISA_v2_3.pdf Simple RISC ISA v.2.3] | ||
# [http://wiki.dcae.pub.ro/images/a/a2/DSD_Project_RISC1_MicroArch_v1_0.pdf Pipeline implementation of the Simple RISC Processor v.1.0] | # [http://wiki.dcae.pub.ro/images/a/a2/DSD_Project_RISC1_MicroArch_v1_0.pdf Pipeline implementation of the Simple RISC Processor v.1.0] | ||
# [http://wiki.dcae.pub.ro/images/0/07/DSD_Project_RISC4_MicroArch_v1_0.pdf Superscalar implementation of the Simple RISC Processor v1.0] | |||
== Assignments == | == Assignments == | ||
Versiunea de la data 20 decembrie 2016 14:12
Design Specifications
- Simple RISC ISA v.2.3
- Pipeline implementation of the Simple RISC Processor v.1.0
- Superscalar implementation of the Simple RISC Processor v1.0
Assignments
- Sequential processor golden model
- Step by step design of the pipelined Simple RISC Processor
- Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)
Resources
- Introduction to Verilog
- Vivado Design Suite Evaluation and WebPACK (Vivado HL WebPACK is free)
