Digital Systems Design - Project: Diferență între versiuni
De la WikiLabs
Jump to navigationJump to search
| Linia 6: | Linia 6: | ||
== Assignments == | == Assignments == | ||
=== First semester === | ==== First semester ==== | ||
# [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model] | # [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model] | ||
# [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor] | # [http://wiki.dcae.pub.ro/images/e/e1/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor] | ||
# [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)] | # [http://wiki.dcae.pub.ro/images/9/9d/2016_step_by_step_tomasulo1.txt Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)] | ||
# [http://wiki.dcae.pub.ro/images/8/8b/Step_by_step_thornton2.txt Step by step design of the superscalar Simple RISC Processor - B (Register renaming)] | # [http://wiki.dcae.pub.ro/images/8/8b/Step_by_step_thornton2.txt Step by step design of the superscalar Simple RISC Processor - B (Register renaming)] | ||
=== Second semester === | ==== Second semester ==== | ||
# [http://wiki.dcae.pub.ro/images/b/bd/Step_by_step_thornton3.txt Step by step design of the superscalar Simple RISC Processor - C (Instruction window)] | # [http://wiki.dcae.pub.ro/images/b/bd/Step_by_step_thornton3.txt Step by step design of the superscalar Simple RISC Processor - C (Instruction window)] | ||
Versiunea de la data 23 februarie 2017 16:41
Design Specifications
- Simple RISC ISA v.2.3
- Pipeline implementation of the Simple RISC Processor v.1.0
- Superscalar implementation of the Simple RISC Processor v1.0
Assignments
First semester
- Sequential processor golden model
- Step by step design of the pipelined Simple RISC Processor
- Step by step design of the superscalar Simple RISC Processor - A (Parallel execution)
- Step by step design of the superscalar Simple RISC Processor - B (Register renaming)
Second semester
Resources
- Introduction to Verilog
- Vivado Design Suite Evaluation and WebPACK (Vivado HL WebPACK is free)
