RC4 Stream Cypher

Objective

Create a PLB peripheral for RC4 encryption and test attained acceleration when compared to a processor-only RC4 implementation.

References

http://en.wikipedia.org/wiki/RC4

Requirements

1. Implement a circuit for RC4 acceleration in Verilog (integrated within a user_logic.v peripheral template)
2. Implement a test-bench for the Verilog code
3. Analyze FPGA resource utilization of your circuit
4. Create an XPS system which uses the RC4 peripheral, implement the system and export it to SDK
5. Create a C code project for processor-only RC4 encryption and test speed
6. Create a C code project for accelerated RC4 encryption and test speed