SHA-1 Hash

Objective

Create a PLB peripheral for SHA-1 hashing and test attained acceleration when compared to a processor-only SHA-1 implementation.

References

http://en.wikipedia.org/wiki/Sha-1

Requirements

1. Implement a circuit for SHA-1 hash acceleration in Verilog (integrated within a user_logic.v peripheral template)
2. Implement a test-bench for the Verilog code
3. Analyze FPGA resource utilization of your circuit
4. Create an XPS system which uses the SHA-1 peripheral, implement the system and export it to SDK
5. Create a C code project for processor-only SHA-1 hashing and test speed
6. Create a C code project for accelerated SHA-1 hashing and test speed