Sorting Network

Objective

Create a PLB peripheral for sorting arrays of 32-bit integers. Test attained acceleration when compared to a processor-only sorter.

References

http://en.wikipedia.org/wiki/Sorting_algorithm

Requirements

1. Implement a circuit for sorting in Verilog (integrated within a user_logic.v peripheral template)
2. Implement a test-bench for the Verilog code
3. Analyze FPGA resource utilization of your circuit for different sizes of input vector (e.g, 8-16-32-128 integers)
4. Create an XPS system which uses the sorting peripheral and determine what is the maximum size of input arrays on the Nexys-2 Board
5. Implement the system and export it to SDK
6. Create a C code project for processor-only sorting and test speed. Explain your choice of sorting algorithm.
7. Create a C code project for accelerated sorting and test speed.