Sum of Absolute Differences

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Objective

Create a PLB peripheral for calculating the sum of absolute differences (SAD) on arrays of 32-bit integers. Test attained acceleration when compared to a processor-only SAD implementation.

References

http://en.wikipedia.org/wiki/L1_norm

Requirements

  1. Implement a circuit for SAD in Verilog (integrated within a user_logic.v peripheral template)
  2. Implement a test-bench for the Verilog code
  3. Analyze FPGA resource utilization of your circuit for different sizes of input vector (e.g, 8-16-32-128 integers)
  4. Create an XPS system which uses the SAD peripheral and determine what is the maximum size of input arrays on the Nexys-2 Board
  5. Implement the system and export it to SDK
  6. Create a C code project for processor-only SAD on arrays of 1024 integers, and test speed.
  7. Create a C code project for accelerated SAD on arrays of 1024 integers, and test speed.