Vizualizare sursă pentru „Sorting Network”

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== Objective == Create a PLB peripheral for sorting arrays of 32-bit integers. Test attained acceleration when compared to a processor-only sorter. == References == http://en.wikipedia.org/wiki/Sorting_algorithm == Requirements == # Implement a circuit for sorting in Verilog (integrated within a user_logic.v peripheral template) # Implement a test-bench for the Verilog code # Analyze FPGA resource utilization of your circuit for different sizes of input vector (e.g, 8-16-32-128 integers) # Create an XPS system which uses the sorting peripheral and determine what is the maximum size of input arrays on the Nexys-2 Board # Implement the system and export it to SDK # Create a C code project for processor-only sorting and test speed. Explain your choice of sorting algorithm. # Create a C code project for accelerated sorting and test speed.

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