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== Objective == Create a PLB peripheral for calculating the sum of absolute differences (SAD) on arrays of 32-bit integers. Test attained acceleration when compared to a processor-only SAD implementation. == References == http://en.wikipedia.org/wiki/L1_norm == Requirements == # Implement a circuit for SAD in Verilog (integrated within a user_logic.v peripheral template) # Implement a test-bench for the Verilog code # Analyze FPGA resource utilization of your circuit for different sizes of input vector (e.g, 8-16-32-128 integers) # Create an XPS system which uses the SAD peripheral and determine what is the maximum size of input arrays on the Nexys-2 Board # Implement the system and export it to SDK # Create a C code project for processor-only SAD on arrays of 1024 integers, and test speed. # Create a C code project for accelerated SAD on arrays of 1024 integers, and test speed.

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