Diferență între revizuiri ale paginii „Digital Systems Design - Project”
De la WikiLabs
Jump to navigationJump to search| Linia 7: | Linia 7: | ||
# [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model] | # [http://wiki.dcae.pub.ro/images/2/23/Golden_model.txt Sequential processor golden model] | ||
| + | # [http://wiki.dcae.pub.ro/images/2/23/Step_by_step_pipeline.txt Step by step design of the pipelined Simple RISC Processor ] | ||
== Resources == | == Resources == | ||
Versiunea de la data 1 noiembrie 2016 15:05
Design Specifications
Assignments
Resources
- Introduction to Verilog
- Vivado Design Suite Evaluation and WebPACK (Vivado HL WebPACK is free)
