Diferență între revizuiri ale paginii „Digital Integrated Circuits (seminar)”
De la WikiLabs
Jump to navigationJump to searchCbira (discuție | contribuții) (Pagină nouă: Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student w...) |
Cbira (discuție | contribuții) |
||
| Linia 3: | Linia 3: | ||
* [[CID Seminar 1]] - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation) | * [[CID Seminar 1]] - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation) | ||
* [[CID Seminar 2]] - Conditioned instructions, using the 'always' instruction to define combinational circuits | * [[CID Seminar 2]] - Conditioned instructions, using the 'always' instruction to define combinational circuits | ||
| − | * [[ | + | * [[DIC Seminar 3]] - Sequential circuits (clock signal, '''always''' and ''' initial ''' vs. '''assign''' |
* [[CID Seminar 4]] - Numerals and counting circuits | * [[CID Seminar 4]] - Numerals and counting circuits | ||
* [[CID Seminar 5]] - Description of memories in Verilog | * [[CID Seminar 5]] - Description of memories in Verilog | ||
Versiunea de la data 26 aprilie 2018 07:20
Starting from the notions presented in the course, the Integrated Digital Circuit introduces the notion of hardware description language (HDL) and aims to familiarize the student with Verilog language, as well as digital circuits synthesis and simulation (QuartusII or ModelSim) .
- CID Seminar 1 - Introduction to Verilog (variables, blocks, test modules, functional modules and instantiation)
- CID Seminar 2 - Conditioned instructions, using the 'always' instruction to define combinational circuits
- DIC Seminar 3 - Sequential circuits (clock signal, always and initial vs. assign
- CID Seminar 4 - Numerals and counting circuits
- CID Seminar 5 - Description of memories in Verilog
- CID Seminar 6 - Finite automata
You can dowload the programs used on the Altera website:
https://dl.altera.com/13.0sp1/?edition=web
