DIC Lab Work 4
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Versiunea din 11 aprilie 2018 23:46, autor: Cbira (discuție | contribuții)
Notions and Knowledge Required
- Boolean logic and numbering systems
- Syntax Verilog
- Using the Altera Quartus II Synthesis Program
- List of pins for plate DE1
- Sequential Circuits, Counter
- Pulse generator with variable filling factor
Example
Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable fill factor signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator.
Exercise
Build a circuit that instantiates 8 variable fill factor signal generators to form a LEDG7-LEDG0 intensity ramp with the following features:
- LEDG0 intensity, denoted I LEDG0 is determined by SW7-SW0
- The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships):
- #I LEDG0 & lt; I LEDG1 & lt; I LEDG2 & lt; I LEDG3 & lt; I LEDG4 & lt; I LEDG5 & lt; I LEDG6 & lt; I LEDG7
- #I LEDG0 & gt; I LEDG1 & lt; I LEDG2 & lt; I LEDG3 & lt; I LEDG4 & lt; I LEDG5 & lt; I LEDG6 & lt; I LEDG7
- #I LEDG0 & gt; I LEDG1 & gt; I LEDG2 & lt; I LEDG3 & lt; I LEDG4 & lt; I LEDG5 & lt; I LEDG6 & lt; I LEDG7
- #I LEDG0 & gt; I LEDG1 & gt; I LEDG2 & gt; I LEDG3 & lt; I LEDG4 & lt; I LEDG5 & lt; I LEDG6 & lt; I LEDG7
- #I LEDG0 & gt; I LEDG1 & gt; I LEDG2 & gt; I LEDG3 & gt; I LEDG4 & lt; I LEDG5 & lt; I LEDG6 & lt; I LEDG7
- #I LEDG0 & gt; I LEDG1 & gt; I LEDG2 & gt; I LEDG3 & gt; I LEDG4 & gt; I LEDG5 & lt; I LEDG6 & lt; I LEDG7
- #I LEDG0 & gt; I LEDG1 & gt; I LEDG2 & gt; I LEDG3 & gt; I LEDG4 & gt; I LEDG5 & gt; I LEDG6 & lt; I LEDG7
- #I LEDG0 & gt; I LEDG1 & gt; I LEDG2 & gt; I LEDG3 & gt; I LEDG4 & gt; I LEDG5 & gt; I LEDG6 & gt; I LEDG7
Bonus Exercise
Make a circuit that then turns off a led gradually, using a variable fill factor generator.
