Verilog EN

Modules (synthesizable)

The Verilog language is structured on modules. Each module represents a circuit that implements a certain function. For example, a module may be a summation, ie a circuit that has two entries specifying the two operands and an output representing the result of the assembly. The content of the module is the (structural or behavioral) description of the gates that computes the sum of the two entries. Therefore, the definition of a Verilog module has two parts:

• interface - the list of all the input and output ports of the circuit, specified by name and size;
• implementation - actual circuit description using input values ​​to calculate output values;

Verilog Module Interface

The Adder module interface is shown below. ' Note: ' As in the decimal system, where the sum of two numbers' 'n digits needs' n '=18), and in the binary system, the sum of two n bits will be on' 'n + 1' bits.

Representation of the Adder module (black box)

module Adder (
    output [4: 0] out,
    input [3: 0] in0,
    input [3: 0] in1
)

//implementation

endmodule

The keywords modules 'and endmodule ' 'are used to start and end defining a module. Immediately after the keyword ' 'module follows the module name.

' 'Convention: The name of a module will begin with a large letter.

After defining the module name, the list of ports, placed between round brackets' 'and separated by comma follows. Accepted keywords are ' 'output (representing an output port), ' 'input (representing an input port) and ' 'inout' '(representing a bidirectional port).

' 'Tip: . They introduce Tri-state Buffer elements that are ineffective. A more efficient alternative is to define two ports, one input and one output, with similar names (ex: data_in and data_out ).

' 'Convention: First the outputs, then the inputs of a module are defined.

' 'Convention: ' module ' '.

According to the port type, it follows its size, specified in the bit indexes, where the least significant bit has the index 0. For example, a 4 bit signal will have the following specification: [3: 0] significantly has index 3, least significant 0, total 4 bits). ' 'Note: One-bit signals lack the size specification:

input signal_de_un_bit,
<syntaxhighlight>

After the list of ports in brackets, the interface definition ends with the ''';''' character.

<!--
#'''' 'Remark:''''' There are non-synthesizable modules (which do not have logical gaps), which are used as test programs in simulation environments and are called test modules. These modules have no input and output ports and are used only to give the input port values ​​of the module to be tested, and to check the values ​​on the output ports of the module. For these modules, the list of ports and their associated parentheses are missing:
<syntaxhighlight lang="verilog">
Module TestModule;

//implementation

endmodule

-->

Implementing Verilog Modules

The implementation of Verilog modules is done through blocks. These blocks may or may not correspond to a physical scent. If all blocks of a module have a correspondent in a physical circuit, then the module is synthesizable and can be transformed into a physical circuit. Blocks that can generate synthesizable constructions are of four types:

• blocks assign
• blocks always
• Instance blocks
• blocks generated

In addition, Verilog can define threads (wire) and registers (reg).

Blocks that are always unintelligible and are used exclusively for simulation:

• blocks initial

Remark: Not any block assign or always is synthesizable. There are syntactic constructs that do not have a correspondent in the circuit. These blocks can be simulated but can not be used to program an FPGA board.

Note: The order of blocks in a module does not matter.