DIC Lab Work 4

Notions and Knowledge Required

• Boolean logic and numbering systems
• Syntax Verilog
• Using the Altera Quartus II Synthesis Program
• List of pins for plate DE1
• Sequential Circuits, Counter
• Pulse generator with variable filling factor

Example

Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable fill factor signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator.

Exercise

Build a circuit that instantiates 8 variable fill factor signal generators to form a LEDG7-LEDG0 intensity ramp with the following features:

• LEDG0 intensity, denoted I _LEDG0 is determined by SW7-SW0
• The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships):
• #I _LEDG0 & lt; I _LEDG1 & lt; I _LEDG2 & lt; I _LEDG3 & lt; I _LEDG4 & lt; I _LEDG5 & lt; I _LEDG6 & lt; I _LEDG7
• #I _LEDG0 & gt; I _LEDG1 & lt; I _LEDG2 & lt; I _LEDG3 & lt; I _LEDG4 & lt; I _LEDG5 & lt; I _LEDG6 & lt; I _LEDG7
• #I _LEDG0 & gt; I _LEDG1 & gt; I _LEDG2 & lt; I _LEDG3 & lt; I _LEDG4 & lt; I _LEDG5 & lt; I _LEDG6 & lt; I _LEDG7
• #I _LEDG0 & gt; I _LEDG1 & gt; I _LEDG2 & gt; I _LEDG3 & lt; I _LEDG4 & lt; I _LEDG5 & lt; I _LEDG6 & lt; I _LEDG7
• #I _LEDG0 & gt; I _LEDG1 & gt; I _LEDG2 & gt; I _LEDG3 & gt; I _LEDG4 & lt; I _LEDG5 & lt; I _LEDG6 & lt; I _LEDG7
• #I _LEDG0 & gt; I _LEDG1 & gt; I _LEDG2 & gt; I _LEDG3 & gt; I _LEDG4 & gt; I _LEDG5 & lt; I _LEDG6 & lt; I _LEDG7
• #I _LEDG0 & gt; I _LEDG1 & gt; I _LEDG2 & gt; I _LEDG3 & gt; I _LEDG4 & gt; I _LEDG5 & gt; I _LEDG6 & lt; I _LEDG7
• #I _LEDG0 & gt; I _LEDG1 & gt; I _LEDG2 & gt; I _LEDG3 & gt; I _LEDG4 & gt; I _LEDG5 & gt; I _LEDG6 & gt; I _LEDG7

Bonus Exercise

Make a circuit that then turns off a led gradually, using a variable fill factor generator.