Digital Systems Design - Project

Design Specifications

1. Simple RISC ISA v.2.3
2. Pipeline implementation of the Simple RISC Processor v.1.0

Assignments

1. Sequential processor golden model

Resources

• Introduction to Verilog
• Vivado Design Suite Evaluation and WebPACK (Vivado HL WebPACK is free)

Announcements

Digilent Design Contest 13th Edition