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Jump to navigationJump to search- 14 septembrie 2026 06:22 dif ist +43.145 N Lab 5 Pagină nouă: = Lab 5 — Project Development I = == Objectives == This laboratory marks the transition from language-oriented laboratories to supervised project development. The main objecti... actuală
- 14 septembrie 2026 06:15 dif ist +46.970 N Lab 4 Pagină nouă: = Lab 4 — Testing, Debugging and Software Quality = == Objectives == This laboratory introduces software testing and quality practices for Python projects. Students already kn... actuală
- 14 septembrie 2026 06:07 dif ist +43.096 N Lab 3 Pagină nouă: = Lab 3 — Modules, Packages, Files, Exceptions and Type Hints = == Objectives == This laboratory moves from individual Python scripts and classes to the structure of complete P... actuală
- 14 septembrie 2026 06:01 dif ist +41.434 N Lab 2 Pagină nouă: = Lab 2 — Object-Oriented Programming in Python = == Objectives == This laboratory introduces object-oriented programming in Python to students who already know object-oriented... actuală
- 14 septembrie 2026 05:54 dif ist -190 Python Project →Python Project actuală
- 14 septembrie 2026 05:54 dif ist +2.814 Python Project
- 14 septembrie 2026 05:51 dif ist -2.207 Lab 1 →Lab 1 — Python for C/C++ Programmers actuală
- 14 septembrie 2026 05:46 dif ist -300 Lab 1 →10. Comparison operators
- 14 septembrie 2026 05:40 dif ist -149 Lab 1 →9. Boolean operators
- 14 septembrie 2026 05:35 dif ist -9 Lab 1 →8. Conditional statements
- 14 septembrie 2026 05:33 dif ist +30 Lab 1 →7. Reading input
- 14 septembrie 2026 05:32 dif ist +5 Lab 1 →6. Printing values
- 14 septembrie 2026 05:30 dif ist +233 Lab 1 →5. Arithmetic operators
- 14 septembrie 2026 05:27 dif ist +15 Lab 1 →4. Constants
- 14 septembrie 2026 05:24 dif ist -614 Lab 1 →3. Variables and types
- 14 septembrie 2026 05:22 dif ist +37.133 Lab 1 →Lab 1 — Python for C/C++ Programmers
- 14 septembrie 2026 05:20 dif ist +7.793 N Lab 1 Pagină nouă: = Lab 1 — Python for C/C++ Programmers = == Objectives == The purpose of this laboratory is to introduce Python to students who already have experience with procedural programm...
- 14 septembrie 2026 05:20 dif ist +9 N Python Project Pagină nouă: Lab 1
- 14 septembrie 2026 05:20 dif ist +21 Pagina principală →Platforme de aplicatii sau laborator actuală
- 8 aprilie 2026 11:20 dif ist +24 Circuite Integrate Digitale →Scopul laboratorului actuală
- 17 martie 2026 16:21 dif ist +2 FPGA Student Classroom tutorial →FAQ actuală
- 17 martie 2026 16:21 dif ist +219 FPGA Student Classroom tutorial →FAQ
- 25 martie 2025 20:16 dif ist +471 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup actuală
- 25 martie 2025 20:14 dif ist +1 N Fișier:Clock summary.png.png actuală
- 10 martie 2025 18:09 dif ist -121 VPN Tutorial - en →Downloading and Installing WireGuard actuală
- 9 martie 2025 15:05 dif ist +102 Reconfigurable Computing →Useful resources actuală
- 9 martie 2025 13:13 dif ist +391 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:12 dif ist +1 N Fișier:Summary.png actuală
- 9 martie 2025 13:09 dif ist +163 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:08 dif ist +1 N Fișier:Source Files.png actuală
- 9 martie 2025 13:04 dif ist +91 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:03 dif ist -2 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:03 dif ist +49 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:03 dif ist -4 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:02 dif ist +8 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:02 dif ist -6 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:02 dif ist +271 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 13:00 dif ist +1 N Fișier:New prj.png actuală
- 9 martie 2025 12:55 dif ist +41 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 9 martie 2025 12:55 dif ist +1 N Fișier:Vitis hls new prj.png actuală
- 8 martie 2025 16:16 dif ist +92 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 8 martie 2025 16:15 dif ist -3 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 8 martie 2025 16:15 dif ist +10 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 8 martie 2025 16:15 dif ist +58 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Setup
- 8 martie 2025 16:15 dif ist +1 N Fișier:Vitis.png actuală
- 8 martie 2025 16:12 dif ist +394 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation
- 8 martie 2025 16:10 dif ist -59 Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation →Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation
- 8 martie 2025 16:09 dif ist +467 N Lab 1 - Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation Pagină nouă: = Intro to High Level Synthesis. Simulation. Co-simulation. RTL generation = High-Level Synthesis (HLS) is a design methodology that enables hardware description at a higher level...
- 8 martie 2025 15:13 dif ist +53 FPGA Student Classroom tutorial →Step 1 - VPN
- 8 martie 2025 15:13 dif ist -18 FPGA Student Classroom tutorial
