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| − | == Notions and Knowledge | + | == Required Notions and Knowledge == |
| − | * [[Introduction. | + | * [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]] |
| − | * Syntax [[Verilog_EN]] | + | * Verilog Syntax [[Verilog_EN]] |
| − | * [[ | + | * [[Quartus_II_tutorial | Using the Altera Quartus II Synthesis Program]] |
| − | * [http://wiki.dcae.pub.ro/images/f/fc/ | + | * [http://wiki.dcae.pub.ro/images/f/fc/Pinii_la_care_sunt_conectati_dispozitivele_I-O_pe_placa_experimentala_DE1.pdf List of pins for DE1 board], [http://wiki.dcae.pub.ro/images/3/37/Pin_Assignments_Cyclone_V_.pdf List of pins for DE1-SoC board] |
* [[Sequential Circuits]], [[Counter]] | * [[Sequential Circuits]], [[Counter]] | ||
| − | * [[Pulse generator with variable | + | * [[Pulse generator with variable duty cycle]] |
== Example == | == Example == | ||
| − | Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable | + | Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable duty cycle signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator. |
== Exercise == | == Exercise == | ||
| − | Build a circuit that instantiates 8 variable | + | Build a circuit that instantiates 8 variable duty cycle signal generators to form a LEDG7-LEDG0 intensity ramp with the following features: |
* LEDG0 intensity, denoted I <sub> LEDG0 </sub> is determined by SW7-SW0 | * LEDG0 intensity, denoted I <sub> LEDG0 </sub> is determined by SW7-SW0 | ||
* The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships): | * The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships): | ||
| Linia 28: | Linia 28: | ||
== Bonus Exercise == | == Bonus Exercise == | ||
| − | + | Build a circuit that then turns off a led gradually, using a variable duty cycle generator. | |
Versiunea curentă din 30 mai 2018 09:32
Required Notions and Knowledge
- Boolean logic and numbering systems
- Verilog Syntax Verilog_EN
- Using the Altera Quartus II Synthesis Program
- List of pins for DE1 board, List of pins for DE1-SoC board
- Sequential Circuits, Counter
- Pulse generator with variable duty cycle
Example
Make a circuit that turns on LEDG7 with a variable intensity controlled by a value set by the SW7-SW0 switches using a variable duty cycle signal generator based on an 8-bit counter. The numerator will be described as a separate Verilog mode, and will be instantiated in the signal generator.
Exercise
Build a circuit that instantiates 8 variable duty cycle signal generators to form a LEDG7-LEDG0 intensity ramp with the following features:
- LEDG0 intensity, denoted I LEDG0 is determined by SW7-SW0
- The LEDG0-7 intensities respect one of the following relationships (the teacher will assign each of the students one of the following relationships):
- I LEDG0 < I LEDG1 < I LEDG2 < I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
- I LEDG0 > I LEDG1 < I LEDG2 < I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
- I LEDG0 > I LEDG1 > I LEDG2 < I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
- I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 < I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
- I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 < I LEDG5 < I LEDG6 < I LEDG7
- I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 > I LEDG5 < I LEDG6 < I LEDG7
- I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 > I LEDG5 > I LEDG6 < I LEDG7
- I LEDG0 > I LEDG1 > I LEDG2 > I LEDG3 > I LEDG4 > I LEDG5 > I LEDG6 > I LEDG7
Bonus Exercise
Build a circuit that then turns off a led gradually, using a variable duty cycle generator.
