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== Notions and Knowledge Required ==
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== Required Notions and Knowledge ==
  
 
* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]]
 
* [[Introduction._Verilog_HDL_(Verilog_syntax)#Numbers_and_symbols._Numbering_Bases|Boolean logic and numbering systems]]
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* It will describe in Verilog a 16x4b RAM with a read-write port. Reading is synchronous.
 
* It will describe in Verilog a 16x4b RAM with a read-write port. Reading is synchronous.
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* The necessary debugging to connect will be written
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* The necessary pin connections will be written
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** Address to SW7-4 and date of entry to SW3-0.
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** the address to SW7-4 and date of entry to SW3-0.
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** writing activation signal at one of the buttons (KEY0 ... KEY3).
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** the write enable signal at one of the buttons (KEY0 ... KEY3).
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** Output memory at LEDR3-0.
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** the output at LEDR3-0.
 
** memory clock input to one of the DE1 plate oscillators.
 
** memory clock input to one of the DE1 plate oscillators.
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* Schedule the FPGA board, and using the switches and buttons on the board, write 3, 6, and 10 with the values ​​2, 1 and 7, then read them in the same order. Notice, using the LEDs of the board, if the memory has been stored.
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* Program the FPGA, and using the switches and buttons on the board, write 3, 6, and 10 with the values ​​2, 1 and 7, then read them in the same order. Notice, using the LEDs of the board, if the memory has been written.
  
 
== Exercise ==
 
== Exercise ==
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     input clk,
 
     input clk,
 
     output reg [31: 0] cnt
 
     output reg [31: 0] cnt
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)
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);
  
 
always @ (posedge clk) cnt <= cnt + 1;
 
always @ (posedge clk) cnt <= cnt + 1;
  
 
endmodule
 
endmodule
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</syntaxhighlight>
  
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ROM modules (
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<syntaxhighlight lang="verilog">
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module ROM(
 
     input [3: 0] in,
 
     input [3: 0] in,
 
     output reg [3: 0] out
 
     output reg [3: 0] out
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)
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);
  
 
always @ (in)
 
always @ (in)
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     houses (in)
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     case (in)
 
         0: out=4'b1010;
 
         0: out=4'b1010;
 
         1: out=4'b0110;
 
         1: out=4'b0110;
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endmodule
 
endmodule
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<syntaxhighlight>
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</syntaxhighlight>
  
 
* Write the constraints required to connect the TOP module ports:
 
* Write the constraints required to connect the TOP module ports:
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** ADR at SW3-0,
 
** ADR at SW3-0,
 
** WEN la KEY3,
 
** WEN la KEY3,
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** DOED to LEDR3-0,
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** DOUT to LEDR3-0,
 
** clock input at CLOCK_50.
 
** clock input at CLOCK_50.
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* Schedule the FPGA board; Write the RAM with the values ​​required to produce DOUT a sequence of numbers indicated by the teacher.
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* Program the FPGA board; Write the RAM with the values ​​required to produce DOUT a sequence of numbers indicated by the teacher.
  
 
== Submission of Exercises ==
 
== Submission of Exercises ==

Versiunea curentă din 30 mai 2018 09:36

Required Notions and Knowledge

Example

  • It will describe in Verilog a 16x4b RAM with a read-write port. Reading is synchronous.
  • The necessary pin connections will be written
    • the address to SW7-4 and date of entry to SW3-0.
    • the write enable signal at one of the buttons (KEY0 ... KEY3).
    • the output at LEDR3-0.
    • memory clock input to one of the DE1 plate oscillators.
  • Program the FPGA, and using the switches and buttons on the board, write 3, 6, and 10 with the values ​​2, 1 and 7, then read them in the same order. Notice, using the LEDs of the board, if the memory has been written.

Exercise

  • Describe in Verilog a 16x4b RAM with two ports:
    • A write-only sync port with the following signals:
      • WR_ADDR - the address you write
      • WR_EN - write command
      • WR_DATA - written data
    • A read-only read-only port with the following signals:
      • RD_ADDR - read address
      • RD_DATA - read data
  • The memory will be instantiated in the TOP module as shown below:

Cid lab6.jpg 

module COUNTER (
    input clk,
    output reg [31: 0] cnt
);

always @ (posedge clk) cnt <= cnt + 1;

endmodule

module ROM(
    input [3: 0] in,
    output reg [3: 0] out
);

always @ (in)
    case (in)
        0: out=4'b1010;
        1: out=4'b0110;
        2: out=4'b0011;
        3: out=4'b1110;
        4: out=4'b1011;
        5: out=4'b1111;
        6: out=4'b0111;
        7: out=4'b1100;
        8: out=4'b0001;
        9: out=4'b0101;
        10: out=4'b1101;
        11: out=4'b0000;
        12: out=4'b0010;
        13: out=4'b0100;
        14: out=4'b1000;
        15: out=4'b1001;
    endcase

endmodule
  • Write the constraints required to connect the TOP module ports:
    • DIN to SW7-4,
    • ADR at SW3-0,
    • WEN la KEY3,
    • DOUT to LEDR3-0,
    • clock input at CLOCK_50.
  • Program the FPGA board; Write the RAM with the values ​​required to produce DOUT a sequence of numbers indicated by the teacher.

Submission of Exercises

For scoring, the following files will be submitted to the e-mail address indicated by the teacher.

An archive zip

  • All Verilog files (with the .v extension) containing the circuit description
  • A constraint file with the .qsf extension
  • A Quartus project file with the .qpf extension

Note that the archive will only contain files (without directories).

The subject of the email message must follow the [Name] _ [First Name] _ [Group] _Mem example Popescu_Ion_423B_Mem

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